JP3064364B2 - Semiconductor integrated circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit having a protection circuit element.

[Conventional technology]

In recent years, in a semiconductor integrated circuit having complementary MOS transistors, as shown in FIG. 4, an always-off type P-channel MOS transistor and an N-channel MOS transistor are connected in series between a high potential power supply and a low potential power supply as an input protection circuit. A protection circuit in which an internal circuit is connected to the connected drain is used.

In recent years, there is a product that uses a metal silicide layer on the surface of the gate electrode and the source / drain regions to reduce the resistance of the polycrystalline silicon layer to increase the speed. In particular, in products such as gate arrays, the number of contact holes formed on the source / drain regions is limited, so that the circuit speed is often limited by the resistance of the diffusion layer in the source / drain regions. It is necessary to provide a silicide layer on the surface of the substrate to lower the resistance.

Furthermore, impurity ions are implanted through a silicide layer provided on the surface of the source / drain region,
By forming the drain region, there is an advantage that a very shallow diffusion layer required for short channeling can be formed. Therefore, in a gate array or the like, the technique of silicidizing the source / drain has become an indispensable technique.

The input protection circuit as described above is also used for such a product, but if the diffusion layer of the source / drain region constituting the MOS transistor of the input protection circuit is shallow, the strength against electrostatic breakdown is sufficient. Instead, a silicide layer is not provided in the source / drain region of the transistor in the input / output protection unit by adding a photolithography process, and a relatively deep diffusion layer is provided to provide strength against electrostatic breakdown.

[Problems to be solved by the invention]

This conventional semiconductor integrated circuit requires a lithography process for providing a silicide layer in a MOS transistor other than the source / drain region of the MOS transistor of the input / output protection unit, and has a problem that the number of processes increases.

[Means for solving the problem]

The semiconductor integrated circuit according to the present invention comprises a silicide layer provided in a well of a reverse conductivity type provided on a semiconductor substrate of one conductivity type, connected between an internal circuit and a power supply, and having a gate electrode connected to a power supply and a gate electrode connected to a power supply and a source / drain region. A first MOS transistor having
Connected between the MOS transistor and GND and the gate electrode is GN
A second MOS transistor having a gate electrode connected to D and a silicide layer in a source / drain region, and a connection point between the first and second MOS transistors using a reverse conductivity type well provided on the semiconductor substrate as a resistance layer More specifically, a reverse conductivity type well used as a resistance layer has a reverse conductivity type high concentration diffusion layer having a silicide layer on the surface as a contact diffusion layer. Is provided.

〔Example〕

 The present invention will be described with reference to the drawings.

1 (a) and 1 (b) are a plan view and a sectional view taken along line AA 'of a first embodiment of the present invention, and FIG. 2 is a circuit for explaining the first embodiment of the present invention. FIG.

As shown in FIGS. 1 (a), 1 (b) and 2, an N-type well 2 is selectively provided on one main surface of a P-type silicon substrate 1 and selectively provided on the surface of the N-type well 2. A contact region including an N ⁺ -type diffusion layer 4 provided by introducing an N-type impurity and a silicide layer 8 provided on the surface of the N ⁺ -type diffusion layer is formed, and the N-type well 2 is used as a resistance layer. Power supply V is provided by wirings 6 and 7 connected to the contact area through contact holes provided in
Connecting a resistor R between the drain of the P-channel transistor Q _1, N-channel transistor Q ₂ to which connected in series with the bonding pads for the input and output signals between _DD and GND.

Here, the N ⁺ -type diffusion layer 4 provided with the silicide layer 8 is vulnerable to electrostatic breakdown, but is defective because the N ⁺ -type diffusion layer 4 is covered with the N-type well 2 even if it is destroyed. not a also a possibility that the transistors Q _1, Q ₂ is broken as in the prior art to serve as a protective element for transistor Q _1, Q ₂ becomes low. Therefore, transistors Q ₁ and Q ₂
Therefore, it is not necessary to increase the number of photolithography steps for preventing the provision of the silicide layer only in the first step.

FIGS. 3 (a) and 3 (b) are a plan view and a cross-sectional view taken along the line BB 'showing a second embodiment of the present invention.

As shown in FIGS. 3 (a) and 3 (b), the end of the PN junction where the surface of the N-type well 2 and the surface of the P-type silicon substrate 1 are in contact with each other is formed so as to surround the periphery of the N-type well 2. ^It has the same configuration as the first embodiment except that a ⁺ type diffusion layer 9 and a silicide layer 8 are provided.

Here, for negative voltage surge, the transistor
The voltage applied to Q ₁ and Q ₂ is clamped by the forward voltage of the N-type well 2 (1 V or less).
It will be clamped by the reverse breakdown voltage of the N-type well 2. The withstand voltage of the N-type well 2 determined by the N-type well 2 and the P-type silicon substrate 1 is about 80 V, and the protection effect is not sufficient. If the P ⁺ -type diffusion layer 9 is provided, the reverse breakdown voltage is determined by the N-type well 2 and the P ⁺ -type diffusion layer 9 and can be reduced to about 15 V, thereby further increasing the protection ability.

〔The invention's effect〕

As described above, according to the present invention, the first and second MOs are formed by using the opposite conductivity type well provided in the one conductivity type semiconductor substrate as a resistance layer.
By connecting between the connection point of the S transistor and the input / output signal terminal, a silicide layer can be provided in the first and second MOS transistors, and the photolithography process can be simplified.

[Brief description of the drawings]

1 (a) and 1 (b) are a plan view and a sectional view taken along line AA 'of a first embodiment of the present invention, and FIG. 2 is a circuit for explaining the first embodiment of the present invention. FIGS. 3 (a) and 3 (b) are a plan view and a sectional view taken along line BB 'of a second embodiment of the present invention, and FIG. 4 is a circuit for explaining a conventional semiconductor integrated circuit. FIG. 1 ... P-type silicon substrate, 2 ... N-type well, 3,4 ... N
⁺ Type diffusion layer, 5 ... interlayer insulating film, 6, 7 ... wiring, 8 ... silicide layer, 9 ... P ⁺ type diffusion layer, Q ₁ ... P-channel transistor, Q ₂ ... N-channel transistor, R: Resistance.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 27/06 H01L 21/822 H01L 21/8234 H01L 27/04 H01L 27/088

Claims (3)

(57) [Claims] A silicide layer is provided on a gate electrode and a source / drain region provided on a reverse conductivity type well provided on a semiconductor substrate of one conductivity type and connected between an internal circuit and a power supply, and a gate electrode connected to a power supply. A first MOS transistor having a silicide layer provided in a region other than the well and connected between the first MOS transistor and GND, and a gate electrode having a gate electrode connected to GND and a source / drain region. A semiconductor integrated circuit, wherein a second MOS transistor and a reverse conductivity type well provided on the semiconductor substrate are connected as a resistive layer between a connection point between the first and second MOS transistors and an input / output signal terminal. circuit. 2. A high-concentration diffusion layer of one conductivity type is provided on an end of a PN junction between a well of a reverse conductivity type used as a resistance layer and a semiconductor substrate so as to surround the well. Semiconductor integrated circuit. 3. A reverse conductivity type well used as a resistance layer includes:
3. The semiconductor integrated circuit according to claim 1, wherein a reverse-concentration high-concentration diffusion layer having a silicide layer on the surface is provided as a contact diffusion layer.