JPH04122060A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To enable formation of silicide layer in first and second MOS transistors and to simplify photolithography process by connecting a reverse conductivity well as a resistance layer between a connection point of first and second MOS transistors and an input/output signal terminal. CONSTITUTION:An N-type well 2 is selectively provided to one main surface of a P type silicon substrate 1. A contact region is formed, which consists of a silicide layer 8 provided to surfaces of an N<+>-type diffusion layer 4 which is provided by selective introduction of N-type impurities to a surface of the well 2 and an N<+>-type diffusion layer 3, and the N-type well 2 is made a resistance layer. A resistance R is connected between a drain of P-channel transistor TrQ1 and N-channel transistor TrQ2 which are connected in series between a rower supply VDD and GND through wirings 6, 7 connected to a contact region through a contact hole provided to the layer insulating film 5, and a bonding pad for input/ output signal. Thereby, it is possible to provide a silicide layer to TrQ1 and TrQ2 and to simplify photolithography process.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and particularly to a semiconductor integrated circuit having a protection circuit element.

[Conventional technology]

In recent years, in semiconductor integrated circuits having complementary MO8) transistors, normally-off type P-channel MOS transistors and N-channel MO8) transistors are connected between high-potential power supplies and low-potential power supplies as input protection circuits, as shown in Figure 4. A protection circuit is used in which the internal circuit is connected to the drain connected in series with the

Recently, there are products that use metal silicide layers on the surfaces of the gate electrode and source/drain regions to lower the resistance of the polycrystalline silicon layer and increase speed. Particularly in products such as gate arrays, the number of contact holes formed on the source/drain region is limited, so the circuit speed is often restricted by the diffusion layer resistance of the source/drain region. It is necessary to provide a silicide layer on the surface to lower the resistance.

Furthermore, by implanting impurity ions through the silicide layer provided on the surface of the source/drain region to form the source/drain region, it has the advantage of forming a very shallow diffusion layer required for short channel formation. . Therefore, in gate arrays and the like, silicidation technology for sources and drains has become an essential technology.

The input protection circuit described above is also used for such products, but if the diffusion layer in the source train region that constitutes the MOS transistor of the input protection circuit is shallow, it has sufficient strength against electrostatic damage. Instead, a photolithography process is added to provide strength against electrostatic damage by not providing a silicide layer in the source/drain regions of the transistors in the input/output protection section, but by providing a relatively deep diffusion layer.

[Problem to be solved by the invention] This conventional semiconductor integrated circuit has a MOS (input/output protection section)
This method requires a phosphorography process to provide a silicide layer on the MOS transistor (other than the source/train region of the transistor), which poses a problem in that the number of steps increases.

[Means to solve the problem]

and a first layer with a soricite layer in the source train region.
MOS) transistors and transistors other than the wells; transistors of the first and second MOS transistors using opposite conductivity type wells provided on the semiconductor substrate as resistance layers;
) It is configured by connecting between the connection point of the Runsistor and the input pressure signal terminal.

〔Example〕

The present invention will be explained with reference to the drawings.

FIGS. 1(a) and (b) are a plan view and a sectional view taken along line A-A' showing the first embodiment of the present invention, and FIG.
FIG. 2 is a circuit diagram for explaining an embodiment of the present invention.

As shown in Figures 1(a) and (b) and Figure 2, P
An N type well 2 is selectively provided on the entire surface of a type silicon substrate 1, and an N+ type diffused layer 4 and an N1 type diffused layer are provided by selectively introducing N type impurities into the surface of the N type well 2. A contact region made of a silicide layer 8 provided on the surface of the N-type well 2 is formed as a resistance layer, and wirings 6 and 7 are connected to the contact region through contact holes provided in the interlayer insulating film 5.
Therefore, a resistor R is connected between the drains of the P-channel transistor Q1 and the N-channel transistor Q2 connected in series between the power supply VDD and GND, and a bonding pad for input pressure signal.

Here, the N+ type scattered layer 4 provided with the silicide layer 8 is vulnerable to electrostatic damage, but even if this N+ type scattered layer 4 were to be destroyed, it would be defective because it is covered with the N type well 2. Moreover, since it also serves as a protection element for transistors Q + and Q 2 , unlike the conventional example, transistors Q1 . The possibility of Q2 being destroyed becomes lower. Therefore,
There is also no need to increase the number of photolithography steps required to avoid providing a silicide layer only in the transistors Q, Q2.

FIGS. 3(a) and 3(b) are a plan view and a sectional view taken along the line BB', showing a second embodiment of the present invention.

As shown in FIGS. 3(a) and (b), N-type well 2
This is the same as the first embodiment except that a P+ type diffusion layer 9 and a silicide layer 8 are provided to surround the N type well 2 at the end of the PN junction where the surface of the P type silicon substrate 1 is in contact with the surface of the P type silicon substrate 1. They have similar configurations.

Here, for negative voltage surge, transistor Q
1. The voltage applied to Q 2 is clamped at the forward voltage of the N-well 2 (below IV), but for positive voltage surges, it will be clamped at the reverse breakdown voltage of the N-well 2.

The withstand voltage of the N-type well 2 determined by the N-type well 2 and the P-type silicon substrate 1 is about 80V, and the protection effect is not sufficient.

By arranging the P+ type diffusion layer 9, the reverse breakdown voltage can be lowered to about 15V since it is determined by the N type well 2 and the P+ type diffusion layer 9, thereby further increasing the protection ability.

〔Effect of the invention〕

As explained above, the present invention provides first and second MO
S) A silicide layer can be provided on the first and second MOS transistors by connecting between the connection point of the transistor and the input d input signal terminal, which has the effect of simplifying the photolithography process. .

[Brief explanation of the drawing]

FIGS. 1(a) and 1(b) are a plan view and a sectional view taken along line A-A' of the first embodiment of the present invention, and FIG.
A circuit diagram for explaining the embodiment of FIG. 3(a),
(b) is a plan view showing the second embodiment of the present invention and B-B
4 is a circuit diagram for explaining a conventional semiconductor integrated circuit. 1...P type silicon substrate, 2...N type silicon substrate 3.4...N+ type scattered layer 5...
・Interlayer insulating film, 6゜7...Wiring, 8...
・Silicide layer, 9...P+ type diffusion layer, Q+...
...P channel transistor, Q2...N channel transistor, R...resistance.

Claims (1)

[Claims] 1. A silicide layer is provided in a well of an opposite conductivity type provided on a semiconductor substrate of one conductivity type and connected between an internal circuit and a power supply, and a gate electrode and a source/drain region where the gate electrode is connected to a power supply. a first MOS transistor provided in a region other than the well, and a first MOS transistor provided in a region other than the well;
a second MOS transistor having a gate electrode connected between GND and a gate electrode connected to GND, and a silicide layer in the source/drain region, and a reverse conductivity type well provided on the semiconductor substrate as a resistance layer; A semiconductor integrated circuit characterized in that a connection is made between a connection point of a second MOS transistor and an input/output signal terminal. 2. The semiconductor integrated circuit according to claim 1, wherein a high concentration diffusion layer of one conductivity type is provided surrounding the periphery of the well on the end of the PN junction between the semiconductor substrate and the opposite conductivity type well used as a resistance layer. .