JPS60198853A - High withstand voltage resistance element - Google Patents

Abstract

PURPOSE:To obtain a high withstand voltage resistance element by a method wherein a plurality of resistance regions formed in wells are connected in series, thereby enabling to obtain the constitution with which necessary withstand voltage can be obtained. CONSTITUTION:A plurality of N<-> well regions 12 are provided in a P type Si substrate 11, and a high density P type regions 14 are formed in the regions 12. Low density P type resistance layers 18 are formed adjoining to the regions 14. Besides, a high density N type regions 13 are provided in wells 12, and a resistance element is formed by electrically connecting said regions 13 to the regions 14. A high withstand voltage resistance element R can be formed by series-connecting a plurality of said resistance elements. The withstand voltage of the resistance element located in each region 12 is relatively low, but the element R can be accomplished by connecting these resistance elements in series. Further, the regions 12 whereon the element R will be proviced are formed simultaneously with the wells 12. Thus, as the element R has the adaptability with a C-MOS process, it can be formed in one body with a high withstand voltage MOSIC having C-MOS logic.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a high voltage resistance element used in a high voltage semiconductor integrated circuit.

<Technical Background of the Invention> The demand for various terminal devices is increasing, and research is being conducted to make these terminal devices smaller and more efficient.

In particular, the use of ICs for high-voltage circuits has become essential for downsizing and lowering prices of recording and display devices.

Currently, such ICs include high-voltage MO for Gurmekun.
8) A device that integrates a transistor array and a low-voltage four-wire circuit to control it has been put into practical use. However, in order to actually use this IC, it is necessary to externally connect a pull-up element such as a load resistor or a saturation type resistor to each drain electrode of the high-voltage MO8) transistor for sol-down. Therefore, in order to further reduce the size and cost of the entire drive device, it is essential to integrate the pull-up element into an integrated IC.

Furthermore, considering the low power consumption of the entire IC, the control logic circuit is C! A MO8 configuration is desirable, and the pull-up element must be compatible with high voltage MO8 and CMO8760 processes.

<Prior art> In a normal low voltage logic circuit, as an example of integrating a sol-down element and a pull-up element, for example, an E-D configuration (W, N, Carr r J, P, Mize + MO
8/LSI D@sign and Appliaat
ion; Megram-HllllBook Comp
any-1972P 111 ) is well known.

In the configurations E and D, as shown in FIG. 1, the enhancement type MOS transistor N1 is used as a pull-down element, and the disolessian type MOS transistor N2 is used as a true element.

However, in the example shown in FIG. 1, if the power supply voltage VDD is increased, the degradation type MoS ()? Enhancement type MO
The drain voltage of the S transistor Nri, that is, the output voltage VD
There is a disadvantage that the power supply voltage vDD is smaller than the power supply voltage vDD.

Another example is a P-channel MO for pull-up.
8) N-channel MOS for transistor and pulldown
) There is an 0MO8 configuration in which a transistor and a transistor are integrated into an IC (the above-mentioned document pH3).

FIG. 2 shows the cross-sectional structure of the 0MO8 configuration. 1 is a semiconductor substrate made of P-type silicon, 2 is an N-well region made of N-type impurities, 3 is a high-concentration PW region 4 is a high-concentration N-type region, and 5 is a stone gate made of low-resistance polycrystalline silicon. The electrode 6 is an aluminum electrode.

In the example of FIG. 2, the well corresponding to the substrate of the P-channel MO8 is electrically connected to the north of the P-channel MO8, so that no substrate effect occurs. Therefore, a voltage equal to the power supply voltage can be extracted as the drain voltage, ie, the output voltage, of the N-channel MOS transistor.

However, the sol-up element used in the normal 0MO8, that is, the P-channel MO8) transistor, has ■Is it equal to the output voltage? −) It is necessary to apply a voltage. ■For this reason, a large dirt pressure is required.

■Drain breakdown voltage is only about 100V at most, which is a drawback.

<Object of the Invention> The object of the present invention is to eliminate the above-mentioned drawbacks and to provide a high voltage MO8) transistor for pull-down and a CMOS for controlling it.
It is an object of the present invention to provide a sol-up element that can easily integrate a logic circuit into an integrated IC and has high breakdown voltage performance.

<Structure of the Invention> The present invention provides two or more second conductivity type semiconductor substrates in a first conductivity type semiconductor substrate.
A well of a conductivity type is provided, and a first conductivity type of a first conductivity type is provided in the well.
The high concentration region, the second high concentration region, and the first. a resistance layer region of a first conductivity type and a low impurity concentration in contact with the second high concentration region; A high breakdown voltage resistance element is characterized in that the first high concentration region and the second high concentration region of different resistance elements are connected to each other to achieve a high breakdown voltage. .

<Principle of the Invention> In the present invention, the necessary breakdown voltage is ensured by connecting in series a plurality of the resistance regions formed in the well and having a relatively low breakdown voltage. In other words, the voltage applied to the high voltage resistance element is divided and applied to each resistance area, so the number of resistance areas must be selected so that the divided voltage is below the voltage resistance N of the 4m resistor. element can be realized.

Furthermore, in the present invention, as in the example of 0MO8 shown in FIG. 2, the substrate effect does not occur in the resistance region, so the output voltage becomes smaller than the power supply voltage and the load driving ability becomes smaller. There isn't.

This is because the resistive layer region is insulatively isolated from the substrate in the well so that majority carriers flow through the resistive layer region from the first high concentration layer electrically connected to the well. This is because the potential relationship with the second high concentration region can be selected.

That is, even if a reverse bias is applied between the second high concentration region and the well, the first high concentration region and the well can always be kept at the same potential, so that no substrate effect occurs.

Further, the well region can also serve as the well region of the high voltage MOS control CMO 8, and no special process is required.

<Embodiments> Examples of the present invention will be described in detail below with reference to the drawings. Fig. 3 shows a high voltage NMO8) transistor HV-N and a low voltage CMO8) transistor LV-N (NMO8). LV-P(PMO8) and a high voltage resistance element R are formed on the same substrate.

11 is a P-type silicon substrate with a low impurity concentration, for example, 20Ω, and 12 is a surface concentration I X I O/eln N depth of about 1
2 μm N-well region, 13 is a high concentration N type region 14 is a high concentration P type region, 15 is a polycrystalline silicon f-)
Electrodes, 16 is a drain terminal, 17 is an N-type low impurity concentration region with an impurity concentration of approximately 5 x 10"/cm', and 18 is a P-type low impurity concentration region, for example, an impurity concentration of approximately 5 x 10"/cm'.
m" and a thickness of approximately 3,000 mm. The 17.degree.

The N-well region in which the high voltage resistance element R is formed is formed at the same time as the N-well for the low voltage PMO transistor (8).

When using this high voltage resistance element as a load resistor shown in the equivalent circuit of Figure 4, in Figure 3, connect the drain terminal 16 of the high voltage resistance MO8) transistor to the resistance element R.
Aluminum wiring may be used to connect the terminal 20 of the resistor element to the power supply DD.

If the sizes of the two resistive elements are chosen equally, a high voltage (~vD
D) is equally divided into each resistance element, so that a high breakdown voltage can be achieved as a whole.

In this example, the withstand voltage of the resistance element in each well is at most 1
By connecting these in series, we were able to realize a high voltage resistance element with a withstand voltage of 200V.

In addition, in both resistance elements, the P electrode, which plays the role of flowing holes into the P-type resistance layer region, has the same potential as the well, so
No substrate effects occur.

<Effects of the Invention> As described above, according to the present invention, a resistance element having high driving ability and high breakdown voltage can be obtained. In addition, the high voltage resistance element according to the present invention is compatible with ordinary CMOS processing, so it can be easily integrated with CMOS logic and high voltage MO8IC.
It can be converted into C. That is, according to the present invention, by integrating a high-voltage sol-up element and a high-voltage pull-down element into an integrated IC, it is possible to realize an inverter circuit, etc., on an IC, which has not been possible in the past.

[Brief explanation of drawings]

Figure 1 is a low-voltage logic circuit diagram with an E-D configuration; Figure 2 is a cross-sectional view of an 0MO8 configuration; Figure 3 is a cross-sectional view of a high voltage MO8 IC circuit that is a mock-up of the present invention; Figure 4 is , shows an equivalent circuit diagram of a high voltage MO5 circuit. DESCRIPTION OF SYMBOLS 11... P type semiconductor substrate, 12... N type well region, 13... N type high concentration region, 14... P type cavity concentration region, 15... date electrode, 16... drain terminal,
17...N type low impurity concentration region, 18...P type low impurity concentration region, 19.20...High breakdown voltage resistance terminal, R.
...High voltage resistance element. Figure 1 Figure 2

Claims (1)

[Claims] (1) Two or more wells of a second conductivity type are provided in a semiconductor substrate of a first conductivity type, and a first high concentration region and a second high concentration region of the first conductivity type are provided in the well, and the first. A resistance layer region of a first conductivity type and a low impurity concentration is provided in contact with the second high concentration region, and further a high concentration layer of a second conductivity type is provided in the well and is electrically connected to the first high concentration region. A high breakdown voltage resistance element, characterized in that the first high concentration region and the second high concentration region of different resistance elements are connected to each other to provide a high breakdown voltage.