JPS6115593B2 - - Google Patents
Info
- Publication number
- JPS6115593B2 JPS6115593B2 JP53074393A JP7439378A JPS6115593B2 JP S6115593 B2 JPS6115593 B2 JP S6115593B2 JP 53074393 A JP53074393 A JP 53074393A JP 7439378 A JP7439378 A JP 7439378A JP S6115593 B2 JPS6115593 B2 JP S6115593B2
- Authority
- JP
- Japan
- Prior art keywords
- gate
- igfet
- type
- substrate
- junction
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 20
- 239000000758 substrate Substances 0.000 claims description 16
- 230000005669 field effect Effects 0.000 claims description 5
- 101100119059 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) ERG25 gene Proteins 0.000 description 4
- 230000002159 abnormal effect Effects 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 230000003685 thermal hair damage Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Protection Of Static Devices (AREA)
- Amplifiers (AREA)
Description
【発明の詳細な説明】
本発明は保護装置付き半導体装置に関し、特に
半導体基板に設けられた絶縁ゲート電界効果トラ
ンジスタ（以下IGFETと略記する）のゲートを
異常電圧から守る保護装置付き半導体装置に関す
る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device with a protection device, and more particularly to a semiconductor device with a protection device that protects the gate of an insulated gate field effect transistor (hereinafter abbreviated as IGFET) provided on a semiconductor substrate from abnormal voltage.
異常電圧によるIGFETの事故を防止する方法
としては、入力ゲートに抵抗とダイオードを使用
するものが一般的に用いられている。すなわち第
１図にＰチヤンネルIGFETの場合について等価
回路で示すように半導体装置の入力端子１と入力
IGFET２のゲート間に抵抗３（半導体基板に、
それとは逆の導電型の拡散層を設けることが多
い）を接続し、抵抗拡散層と半導体基板間に形成
されるPN接合ダイオード４を介して、この抵抗
３は基板に接続される。これはサージ電圧を抵抗
と容量（前記ダイオード４の容量）で緩和すると
ともに、ダイオードの順方向の立上り電圧または
逆方向のツエナ電圧により異常電圧をクリツプす
るものであるが、最近のように高速動作が要求さ
れる半導体装置においては、抵抗と容量できまる
時定数に制限をうけるため、必ずしも保護が十分
ではなくなつてきている。 A commonly used method to prevent IGFET failures caused by abnormal voltages is to use a resistor and diode at the input gate. In other words, as shown in the equivalent circuit in the case of a P-channel IGFET in Figure 1, the input terminal 1 of the semiconductor device and the input
Resistor 3 (on the semiconductor substrate) between the gate of IGFET2
This resistor 3 is connected to the substrate via a PN junction diode 4 formed between the resistance diffusion layer and the semiconductor substrate. This reduces surge voltage using resistance and capacitance (the capacitance of the diode 4), and clips abnormal voltage using the forward rising voltage of the diode or reverse Zener voltage. In semiconductor devices that require protection, protection is no longer necessarily sufficient because the time constant determined by resistance and capacitance is limited.
また、第２図に等価回路で示すように、ドレイ
ンとゲートを入力IGFET２に接続したデプレツ
シヨン型IGFET５を入力端子１との間に直列に
捜入し、入力端子１に異常電圧が加わるとデプレ
ツシヨン型IGFET５のソースが基板に対して深
く逆バイアスされることにより基板効果が働き、
ただちにカツトオフするというものであるこの方
法は前記のものに比べて極めて優れているがデプ
レツシヨンIGFETのゲートが破壊されることが
ある。 In addition, as shown in the equivalent circuit in Fig. 2, a depletion type IGFET 5 whose drain and gate are connected to the input IGFET 2 is inserted in series with the input terminal 1, and when an abnormal voltage is applied to the input terminal 1, the depletion type IGFET 5 is connected to the input IGFET 2. The substrate effect works because the source of IGFET5 is deeply reverse biased with respect to the substrate.
Although this method of immediate cut-off is much superior to the previous method, the gate of the depletion IGFET may be destroyed.
本発明はこのような事情に鑑みてなされたもの
で、信頼性の改善された高速動作可能な保護装置
付き半導体装置を提供することを目的とする。 The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor device with a protection device that has improved reliability and is capable of high-speed operation.
本発明は、入力端子と入力IGFETのゲート間
に、基板をゲートとするゲート接地型の接合型
FET６を挿入した保護装置付き半導体装置で、
その等価回路を第３図に示す。 The present invention provides a gate-grounded junction type in which the substrate is the gate between the input terminal and the gate of the input IGFET.
A semiconductor device with a protection device inserted with FET6,
The equivalent circuit is shown in FIG.
以下実施例に従つて、本発明を説明すると、第
４図において、ケイ素のようなＮ型半導体基板７
に不純物濃度1015／cm3程度深さ６〜７μｍのＰウ
エル８をイオン注入法等により形成し、さらにＮ
型半導体基板７とＰウエル８の表面部にそれぞれ
１対のP+型領域を形成して入力IGFET２のソー
ス領域９、ドレイン領域１０、接合型FET６の
ドレイン領域１１、ソース領域１２とする。１３
はゲート絶縁膜、１４はフイールド絶縁膜であ
る。入力IGFET２のゲート電極１５は接合型
FET６のドレイン領域１１と接続されている。
接合型FET６のソース電極１７は入力端子１に
接続されている（図示は省略する。）。 The present invention will be described below according to embodiments. In FIG. 4, an N-type semiconductor substrate 7 such as silicon is shown.
A P well 8 with an impurity concentration of 10 15 /cm 3 and a depth of 6 to 7 μm is formed by ion implantation or the like.
A pair of P + type regions are formed on the surface of the type semiconductor substrate 7 and the P well 8, respectively, and serve as the source region 9 and drain region 10 of the input IGFET 2, and the drain region 11 and source region 12 of the junction type FET 6. 13
1 is a gate insulating film, and 14 is a field insulating film. The gate electrode 15 of input IGFET 2 is a junction type
It is connected to the drain region 11 of FET6.
A source electrode 17 of the junction FET 6 is connected to the input terminal 1 (not shown).
接合型FET６の内部抵抗は、入力電圧が０〜
数ボルト程度では比較的低くて、通常の動作に影
響しないが、それ以上に高い電圧が加わると空乏
層がチヤンネル内に拡がつて、ついにはこのチヤ
ンネルをカツトオフしてしまう。従つて入力
IGFET２のゲートは破壊を免かれることができ
る。 The internal resistance of junction FET6 is
A voltage of a few volts is relatively low and does not affect normal operation, but if higher voltages are applied, the depletion layer will expand into the channel and eventually cut it off. therefore input
The gate of IGFET2 can be spared from destruction.
第５図は本発明の他の実施例を示し、Ｐ型拡散
層１８を設けることにより、入力端子１と接続さ
れた金属配線１９と接合型FET６のソース領域
１２間に抵抗を捜入したもので、接合型FET６
近傍で起るブレークダウン時の電流を制限し、こ
の発熱により起こる熱破壊を防ぐ方法を合せて採
ることにより一層保護効果が高まる。 FIG. 5 shows another embodiment of the present invention, in which a resistance is inserted between the metal wiring 19 connected to the input terminal 1 and the source region 12 of the junction FET 6 by providing a P-type diffusion layer 18. So, junction type FET6
The protective effect can be further enhanced by limiting the current during breakdown that occurs in the vicinity and also by taking measures to prevent thermal damage caused by this heat generation.
第６図は本発明の更に他の実施例を示し、第５
図の実施例において、接合型FET６のソース領
域１２とドレイン領域１１の間にN+型チヤンネ
ルストツパ２０を形成したもので、チヤンネルス
トツパは半導体基板１に接続するしないは任意で
あるが、いずれにせよ、ゲートの実効面積は増大
するから保護効果は一層よくなる。 FIG. 6 shows still another embodiment of the present invention, and FIG.
In the embodiment shown in the figure, an N + type channel stopper 20 is formed between the source region 12 and drain region 11 of the junction FET 6, and the channel stopper may be connected to the semiconductor substrate 1 or not. In any case, since the effective area of the gate increases, the protection effect becomes even better.
また相補型のIGFETを形成する場合、基板と
逆の導電型のサブストレート領域を接合型FET
のチヤンネルとして使用すると製造工程上有利と
なる。 In addition, when forming a complementary IGFET, the substrate region of the opposite conductivity type to the substrate is used as a junction FET.
When used as a channel, it is advantageous in the manufacturing process.
なお、以上の実施例において抵抗は、第１図の
従来例における抵抗３より抵抗値において小さく
設定しうる。何となれば、本発明において抵抗は
電流制限のために捜入されたものだからである。 In the above embodiment, the resistance value of the resistor can be set to be smaller than that of the resistor 3 in the conventional example shown in FIG. This is because, in the present invention, the resistor is used to limit the current.
また、主としてＰチヤンネルIGFETについて
説明したが、ＮチヤンネルIGFETあるいはその
双方を同一半導体基板に設けた半導体装置に本発
明を適用しうることは改めて説明するまでもな
い。 Moreover, although the description has mainly been given to a P-channel IGFET, it goes without saying that the present invention can be applied to a semiconductor device in which an N-channel IGFET or both are provided on the same semiconductor substrate.
以上詳細に説明したように、本発明によれば、
保護装置付き半導体装置において高抵抗を用いな
いでよいから動作速度は改善され、接合型FET
を用いているので信頼性が向上する効果がある。 As explained in detail above, according to the present invention,
Since there is no need to use high resistance in semiconductor devices with protection devices, the operating speed is improved, and junction FET
This has the effect of improving reliability.
第１図および第２図はいずれも従来の保護装置
付き半導体装置の等価回路図、第３図は本発明の
保護装置付き半導体装置の等価回路図、第４図な
いし第６図はそれぞれ本発明の実施例を示す断面
図である。
１……入力端子、２……入力IGFET、３……
抵抗、４……ダイオード、５……デプレツシヨン
型IGFET、６……接合型FET、７……Ｎ型半導
体基板、８……Ｐウエル、９，１２……ソース領
域、１０，１１……ドレイン領域、１３……ゲー
ト絶縁膜、１４……フイールド絶縁膜、１５……
ゲート電極、１６……ドレイン電極、１７……ソ
ース電極、１８……Ｐ型拡散層、１９……金属配
線、２０……N+型チヤンネルストツパ。
1 and 2 are equivalent circuit diagrams of a conventional semiconductor device with a protection device, FIG. 3 is an equivalent circuit diagram of a semiconductor device with a protection device of the present invention, and FIGS. FIG. 1...Input terminal, 2...Input IGFET, 3...
Resistor, 4...Diode, 5...Depression type IGFET, 6...Junction type FET, 7...N type semiconductor substrate, 8...P well, 9, 12... Source region, 10, 11... Drain region , 13... Gate insulating film, 14... Field insulating film, 15...
Gate electrode, 16...Drain electrode, 17...Source electrode, 18...P type diffusion layer, 19...Metal wiring, 20...N + type channel stopper.
Claims (1)
果トランジスタを含み、上記電界効果トランジス
タのゲート電極に、基板をゲートの少くとも一部
として有するゲート接地型の接合型電界効果トラ
ンジスタのソース電極を接続し、該接合型電界効
果トランジスタのドレイン電極を入力端子に接続
したことを特徴とする保護装置付き半導体装置。1 Including an insulated gate field effect transistor provided on a semiconductor substrate, the gate electrode of the field effect transistor is connected to the source electrode of a gate-grounded junction field effect transistor having the substrate as at least a part of the gate. A semiconductor device with a protection device, characterized in that a drain electrode of the junction field effect transistor is connected to an input terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7439378A JPS551142A (en) | 1978-06-19 | 1978-06-19 | Semiconductor with protector |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7439378A JPS551142A (en) | 1978-06-19 | 1978-06-19 | Semiconductor with protector |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS551142A JPS551142A (en) | 1980-01-07 |
| JPS6115593B2 true JPS6115593B2 (en) | 1986-04-24 |
Family
ID=13545886
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7439378A Granted JPS551142A (en) | 1978-06-19 | 1978-06-19 | Semiconductor with protector |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS551142A (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5750109A (en) * | 1980-09-10 | 1982-03-24 | Toshiba Corp | High impedance circuit for integrated circuit |
| JPS6211258A (en) * | 1985-07-08 | 1987-01-20 | Nec Corp | Gaas semiconductor integrated circuit |
| US5686751A (en) * | 1996-06-28 | 1997-11-11 | Winbond Electronics Corp. | Electrostatic discharge protection circuit triggered by capacitive-coupling |
| JP5694020B2 (en) * | 2011-03-18 | 2015-04-01 | トランスフォーム・ジャパン株式会社 | Transistor circuit |
-
1978
- 1978-06-19 JP JP7439378A patent/JPS551142A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS551142A (en) | 1980-01-07 |
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