JPH0237112B2 - - Google Patents
Info
- Publication number
- JPH0237112B2 JPH0237112B2 JP56105934A JP10593481A JPH0237112B2 JP H0237112 B2 JPH0237112 B2 JP H0237112B2 JP 56105934 A JP56105934 A JP 56105934A JP 10593481 A JP10593481 A JP 10593481A JP H0237112 B2 JPH0237112 B2 JP H0237112B2
- Authority
- JP
- Japan
- Prior art keywords
- diffusion layer
- protection
- transistor
- gate
- breakdown
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000009792 diffusion process Methods 0.000 claims description 18
- 239000004065 semiconductor Substances 0.000 claims description 11
- 239000012535 impurity Substances 0.000 claims description 4
- 230000015556 catabolic process Effects 0.000 description 10
- 238000010586 diagram Methods 0.000 description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 229910052814 silicon oxide Inorganic materials 0.000 description 8
- 239000000758 substrate Substances 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 3
- 238000001947 vapour-phase growth Methods 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 208000033999 Device damage Diseases 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 230000009993 protective function Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Amplifiers (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Protection Of Static Devices (AREA)
Description
【発明の詳細な説明】
この発明は、絶縁ゲート型電界効果トランジス
タのゲート保護、ならびに保護ダイオードのＰ−
Ｎ接合の破懐を防止できる保護回路を備えた半導
体集積回路装置に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention provides gate protection for insulated gate field effect transistors and P-
The present invention relates to a semiconductor integrated circuit device equipped with a protection circuit that can prevent damage to an N junction.
一般に、半導体集積回路装置は多数の入力およ
び出力端子を有するが、これらの端子には静電
気、過渡現象等のさけることの困難な高電圧が印
加されることがあり、装置破懐の大きな要困の一
つとなつている。このような、高電圧印加による
ゲート絶縁破懐を防止するため、従来は第１図あ
るいは第２図に示すような、保護ダイオードを利
用してゲートにダイオードの耐圧以上の高電圧が
印加されるのを防止する保護回路が設けられてい
る。このような保護回路においては、保護ダイオ
ードの耐圧を低く設定し、ゲートにかかる電圧を
より低くおさえてやることで保護効果を上げるこ
とができる。 Semiconductor integrated circuit devices generally have a large number of input and output terminals, but high voltages that are difficult to avoid due to static electricity, transient phenomena, etc. may be applied to these terminals, which can cause serious problems that can lead to device damage. It has become one of the In order to prevent gate insulation breakdown due to high voltage application, conventionally a protection diode is used to apply a high voltage higher than the withstand voltage of the diode to the gate, as shown in Figure 1 or Figure 2. A protection circuit is provided to prevent this. In such a protection circuit, the protection effect can be increased by setting the withstand voltage of the protection diode low and keeping the voltage applied to the gate lower.
第１図は入力保護回路を示すもので、入力パツ
ド１１に供給された信号は、拡散抵抗Ｒを介して
内部回路を構成するトランジスタTr１のゲート
に供給される。そして、入力パツド１１にサージ
電圧が印加されると、上記拡散抵抗Ｒと半導体基
板とによつて形成されたツエナーダイオードDz
がブレークダウン状態となり、サージ電圧は短絡
されるため、内部回路を構成するトランジスタ
Tr１のゲートは保護される。 FIG. 1 shows an input protection circuit, in which a signal supplied to an input pad 11 is supplied via a diffusion resistor R to the gate of a transistor Tr1 constituting an internal circuit. When a surge voltage is applied to the input pad 11, the Zener diode Dz formed by the diffused resistor R and the semiconductor substrate
enters a breakdown state and the surge voltage is short-circuited, causing the transistors that make up the internal circuit to
The gate of Tr1 is protected.
第２図は出力保護回路を示すもので、内部回路
を構成するトランジスタTr２あるいはTr３の導
通、非導通状態により、その接続点から供給され
た出力信号は、保護抵抗Ｒを介して出力パツド１
２に供給される。そして、この出力パツド１２に
サージ電圧が印加されるとツエナーダイオード
Dzがブレークダウン状態となり、サージ電圧が
短絡されるようにして成る。 Figure 2 shows an output protection circuit. Depending on the conduction or non-conduction state of transistor Tr2 or Tr3 that constitutes the internal circuit, the output signal supplied from the connection point is passed through the protection resistor R to the output pad 1.
2. When a surge voltage is applied to this output pad 12, the Zener diode
Dz is in a breakdown state and the surge voltage is short-circuited.
第３図は、上記保護回路（ツエナーダイオード
Dzおよび保護抵抗Ｒ）の断面構成図で、Ｐ型の
半導体基板１３上に、フイールド反転電位を上げ
るためのイオン注入によるP+１４が設けられる。
そして、この拡散層１４上にシリコン酸化膜１５
が形成され、この酸化膜１５をパターニング後、
N+の拡散領域１６が形成される。このようにし
て形成された基板上にシリコン酸化膜の気相成長
層１７が被覆され、この気相成長層１７をパター
ニング後、パッド、配線等にアルミニウム１８が
蒸着されて成る。ここで、保護抵抗ＲはN+の拡
散層１６、ツエナーダイオードDzはN+の拡散層
１６と半導体基板１３によつてそれぞれ構成され
る。 Figure 3 shows the above protection circuit (Zener diode
In this cross-sectional configuration diagram of Dz and protection resistor R), P + 14 is provided on a P-type semiconductor substrate 13 by ion implantation to increase the field inversion potential.
A silicon oxide film 15 is then formed on this diffusion layer 14.
is formed, and after patterning this oxide film 15,
An N + diffusion region 16 is formed. A vapor phase growth layer 17 of silicon oxide film is coated on the substrate thus formed, and after patterning this vapor phase growth layer 17, aluminum 18 is vapor deposited on pads, wiring, etc. Here, the protective resistor R is constituted by the N + diffusion layer 16, and the Zener diode Dz is constituted by the N + diffusion layer 16 and the semiconductor substrate 13, respectively.
しかし、このような構成の保護回路では、ゲー
ト絶縁破懐は防止できても保護ダイオードのＰ−
Ｎ接合の接合破壊が充分保護できない欠点があ
る。すなわち、第３図に示したようなほぼ均一な
拡散の深さで形成された拡散層１６の場合、コン
タクト部付近のN+領域とフイールド反転電圧を
上げるために設けられたP+領域１４との接合部
１９の耐圧が低い。このため、高電圧印加時にお
ける保護ダイオードDzのブレークダウン時に生
ずる過電流がこの部分１９に集中しやすく、コン
タクト部付近の接合部１９でのジヤンクシヨン破
壊を招き易い。 However, in a protection circuit with such a configuration, although gate insulation breakdown can be prevented, the protection diode's P-
There is a drawback that junction breakdown of the N junction cannot be sufficiently protected. That is, in the case of the diffusion layer 16 formed with a substantially uniform diffusion depth as shown in FIG . The breakdown voltage of the joint 19 is low. Therefore, an overcurrent generated when the protection diode Dz breaks down when a high voltage is applied tends to concentrate in this portion 19, which tends to cause juncture breakdown at the junction 19 near the contact portion.
この発明は、上記のような事情に鑑みてなされ
たもので、その目的とするところは、過大入印加
時のコンタクト近辺のＰ−Ｎ接合での電流集中を
緩和してジヤンクシヨン破壊を防止し、拡散層の
有する保護機能を有効に利用できる半導体集積回
路装置を提供することである。 This invention was made in view of the above-mentioned circumstances, and its purpose is to alleviate current concentration at the P-N junction near the contact when an excessive voltage is applied, and to prevent juncture breakdown. An object of the present invention is to provide a semiconductor integrated circuit device that can effectively utilize the protective function of a diffusion layer.
以下、この発明の一実施例について図面を参照
して説明する。 An embodiment of the present invention will be described below with reference to the drawings.
第４図ａ，ｂはそれぞれその構成を示すもの
で、ａ図はパターン平面図、ｂ図は断面構成図で
ある。すなわち、コンタクトの周囲にデイプレツ
シヨン型トランジスタを配設して高抵抗領域とし
たもので、半導体基板１３上にP+拡散層１４、
シリコン酸化膜１５、およびN+拡散領域１６を
順次形成後、上記N+拡散領域１６と入力パツド
１８とのコンタクト部CHを囲むようにコの字形
にポリシリコンゲートのデイプレツシヨン型トラ
ンジスタTrDを形成する。図において、Poはト
ランジスタTrDのポリシリコンゲート、Ｃはチ
ヤンネルである。 Figures 4a and 4b show the structure thereof, with figure a being a pattern plan view and figure b being a cross-sectional configuration diagram. That is, a depletion type transistor is arranged around the contact to form a high resistance region, and a P + diffusion layer 14,
After sequentially forming the silicon oxide film 15 and the N + diffusion region 16, a U-shaped polysilicon gate depletion transistor TrD is formed so as to surround the contact portion CH between the N + diffusion region 16 and the input pad 18. . In the figure, Po is the polysilicon gate of the transistor TrD, and C is the channel.
通常、高抵抗領域には大きな面積を必要とする
が、例えば第５図ａ，ｂにそれぞれ示すように、
ａ図の負荷抵抗Ｒ２をトランジスタTr４のゲー
トとドレインを短絡して置換することによつて微
小面積で高抵抗を得られるように、トランジスタ
を高抵抗領域として用いることができる。 Normally, a large area is required for a high resistance region, but for example, as shown in Figures 5a and 5b,
By replacing the load resistor R2 in Figure a by shorting the gate and drain of the transistor Tr4, the transistor can be used as a high resistance region so that high resistance can be obtained in a small area.
第６図ａ〜ｅはそれぞれ、上記デイプレツシヨ
ン型トランジスタTrDの形成方法を説明するた
めの図である。すなわち、ａ図に示すように、Ｐ
形の半導体基板１３上にP+領域１４、シリコン
酸化膜１５を順次形成する。そして、トランジス
タTrDのゲート絶縁層となるシリコン酸化膜２
０を形成して、その上にフオトレジスト２１を塗
布し、このフオトレジスト２１をパターニングす
る。さらに、上記パターン形成されたフオトレジ
スト２１の開口部を通してリン（P+31）又はヒ
素（As）のイオン注入を行なう。この状態をｂ
図に示す。次に、フオトレジスト２１を除去し、
マスク形成後エツチングを行なつてトランジスタ
TrDのゲート絶縁層を残して上記イオン注入部
のシリコン酸化膜２０を除去するとｃ図に示すよ
うになる。そして、上記のようにして形成した基
板上にポリシリコン層Poを被覆し、フオトレジ
スト２２を塗布して所定の形状にパターニングを
行なう。この状態をｄ図に示す。次に、トランジ
スタのソース、ドレインとなる部分にN+の不純
物拡散を行なつて、ｅ図に示すようなトランジス
タTrDが構成される。 FIGS. 6a to 6e are diagrams for explaining a method of forming the depletion type transistor TrD, respectively. That is, as shown in figure a, P
A P + region 14 and a silicon oxide film 15 are sequentially formed on a shaped semiconductor substrate 13. Then, a silicon oxide film 2 becomes the gate insulating layer of the transistor TrD.
0 is formed, a photoresist 21 is applied thereon, and this photoresist 21 is patterned. Further, ion implantation of phosphorus (P + 31) or arsenic (As) is performed through the opening of the patterned photoresist 21. This state is b
As shown in the figure. Next, the photoresist 21 is removed,
After mask formation, etching is performed to form a transistor.
When the silicon oxide film 20 in the ion implantation area is removed leaving the gate insulating layer of the TrD, the result is as shown in Figure c. Then, the substrate formed as described above is covered with a polysilicon layer Po, and a photoresist 22 is applied and patterned into a predetermined shape. This state is shown in figure d. Next, N + impurity is diffused into the portions that will become the source and drain of the transistor, thereby forming a transistor TrD as shown in Figure e.
その後、シリコン酸化膜の気相成長層１７、ア
ルミニウムのパツド、配線１８等を形成して成
る。 Thereafter, a vapor phase growth layer 17 of silicon oxide film, aluminum pads, wiring 18, etc. are formed.
このように構成された回路にサージ等の高電圧
が印加された場合、コンタクトの周囲が上記高抵
抗領域で囲まれているため、ダイオードのブレー
クダウンによつて生ずる過電流はこの高抵抗領域
で制限され、コンタクト周辺のＰ−Ｎ接合への過
電流集中を防止することができる。また、内部回
路へは拡散層を介して伝達され、この拡散層によ
つて電位が充分下げられるため、内部回路も充分
に保護することができる。 When a high voltage such as a surge is applied to a circuit configured in this way, the contact is surrounded by the above-mentioned high-resistance region, so the overcurrent generated by diode breakdown will be carried away in this high-resistance region. It is possible to prevent overcurrent from concentrating on the P-N junction around the contact. Further, since the potential is transmitted to the internal circuit via the diffusion layer and the potential is sufficiently lowered by the diffusion layer, the internal circuit can also be sufficiently protected.
第７図ａ，ｂは、上記トランジスタTrDの変
形例を示すもので、ａ図はパターン平面図、ｂ図
は断面構成図である。すなわち、トランジスタ
TrDのゲート絶縁膜２０とシリコン酸化膜１５
を接合配置し、ポリシリコンゲートPoをコンタ
クト側のN+拡散層に接続したもので、このよう
な構成においても上記実施例と同様にコンタクト
周辺のＰ−Ｎ接合への過電流集中を防止でき同様
な効果が得られる。 7a and 7b show a modification of the transistor TrD, in which figure a is a pattern plan view and figure b is a cross-sectional configuration diagram. i.e. transistor
TrD gate insulating film 20 and silicon oxide film 15
The polysilicon gate Po is connected to the N + diffusion layer on the contact side. Even in this configuration, it is possible to prevent overcurrent concentration to the P-N junction around the contact, as in the above embodiment. A similar effect can be obtained.
なお、上記実施例では入力保護回路について説
明したが、同様にして出力保護回路に設けても良
いのはもちろんである。 Although the input protection circuit has been described in the above embodiment, it goes without saying that the output protection circuit may be provided in the same manner.
以上説明したようにこの発明によれば、コンタ
クト周囲にデイプレツシヨン型トランジスタを配
設することにより過電圧印加時の過電流により発
生し易いコンタクト近辺でのジヤンクシヨン破壊
を効果的に防止できる半導体集積回路装置が得ら
れる。 As explained above, according to the present invention, there is provided a semiconductor integrated circuit device that can effectively prevent junction breakdown near the contacts, which is likely to occur due to overcurrent when overvoltage is applied, by arranging depletion type transistors around the contacts. can get.
第１図、第２図はそれぞれ従来の半導体集積回
路装置における入力保護回路および出力保護回路
を示す図、第３図は上記第１図、第２図の回路に
おける保護ダイオードと拡散層のパターン構成例
を示す断面図、第４図ａ，ｂはそれぞれこの発明
の一実施例に係る半導体集積回路装置の入出力保
護回路におけるコンタクト部のパターン平面図お
よびその断面構成図、第５図ａ，ｂはそれぞれ抵
抗素子のチツプ占有面積を説明するための回路
図、第６図ａ〜ｅはそれぞれ第４図ａ，ｂのデイ
プレツシヨン型トランジスタの形成方法を説明す
るための図、第７図ａ，ｂはそれぞれ上記デイプ
レツシヨン型トランジスタの変形構成例を示すパ
ターン平面図および断面構成図である。
TrD……高抵抗領域（デイプレツシヨン形ト
ランジスタ）、CH……コンタクト部。
1 and 2 are diagrams showing an input protection circuit and an output protection circuit, respectively, in a conventional semiconductor integrated circuit device, and FIG. 3 is a pattern configuration of a protection diode and a diffusion layer in the circuit shown in FIGS. 1 and 2 above. A sectional view showing an example, FIGS. 4a and 4b are a pattern plan view of a contact portion in an input/output protection circuit of a semiconductor integrated circuit device according to an embodiment of the present invention, and a sectional configuration diagram thereof, and FIGS. 5a and 5b, respectively. 6A to 6E are circuit diagrams for explaining the chip occupation area of a resistive element, respectively, FIGS. 6A to 6E are diagrams for explaining a method of forming the depletion type transistor of FIGS. 2A and 2B are a pattern plan view and a sectional configuration diagram respectively showing a modified configuration example of the depletion type transistor. TrD...High resistance region (depression type transistor), CH...Contact part.
Claims (1)
保護ダイオードを構成する不純物拡散層を介して
入力あるいは出力し、上記不純物拡散層と配線と
のコンタクト部の不純物拡散層周辺部にデイプレ
ツシヨン型トランジスタから成る高抵抗領域を有
する保護回路を設けたことを特徴とする半導体集
積回路装置。1 Input or output an input signal or an output signal through an impurity diffusion layer constituting a protection resistor and a protection diode, and a high resistance consisting of a depletion type transistor in the periphery of the impurity diffusion layer at the contact area between the impurity diffusion layer and the wiring. A semiconductor integrated circuit device comprising a protection circuit having a region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56105934A JPS587870A (en) | 1981-07-07 | 1981-07-07 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56105934A JPS587870A (en) | 1981-07-07 | 1981-07-07 | Semiconductor integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS587870A JPS587870A (en) | 1983-01-17 |
| JPH0237112B2 true JPH0237112B2 (en) | 1990-08-22 |
Family
ID=14420673
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56105934A Granted JPS587870A (en) | 1981-07-07 | 1981-07-07 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS587870A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03127695U (en) * | 1990-04-03 | 1991-12-24 |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04100106U (en) * | 1991-02-12 | 1992-08-28 | ||
| DE69317004T2 (en) * | 1992-03-26 | 1998-06-10 | Texas Instruments Inc | High voltage structure with oxide insulated source and RESURF drift zone in solid silicon |
-
1981
- 1981-07-07 JP JP56105934A patent/JPS587870A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03127695U (en) * | 1990-04-03 | 1991-12-24 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS587870A (en) | 1983-01-17 |
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