JPS587870A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To prevent a junction breakdown in a semiconductor integrated circuit device by arranging a depletion type Tr around a contact as a high resistance region, and alleviating a current concentration in a P-N junction in the vicinity of the contact at the time of applying an excessively high input. CONSTITUTION:A P<+> type diffused layer 14, an Si oxidized film 15 and an N<+> type diffused region 16 are sequentially formed on a substrate 13, and a depletion type TrD of polysilicon gate P0 is formed in ?-shape to surround a contact CH of the region 16 with an input pad 18. A high resistance region requires a large area, but high resistance is obtained in an ultrafine area by substituting a load resistance T2 for the Tr4 by shortcircuiting the gate and the drain, thereby using the Tr as a high resistance region. In this manner, the junction breakdown at the time of applying an excessively high input can be prevented.

Description

[Detailed Description of the Invention] Jin's device is equipped with a protection circuit that can protect the gate of the insulated gate resistor and prevent the destruction of the P-Nil structure of the protection diode. Regarding equipment.

Semiconductor integrated circuit devices generally have a large number of input and output terminals, but high voltages such as static electricity and transient events may be applied to these terminals, which can cause serious damage to the solder. This is one of the reasons why
In order to prevent gate dielectric breakdown due to voltage application, conventionally an eyelid protection diode was used to prevent high voltage higher than the withstand voltage of the diode from being applied to the gate, as shown in Figure 1 or Figure 2. A wrinkle protection circuit is provided. In such a protection circuit, the protection effect can be increased by setting the withstand voltage of the eyelid protection diode low and keeping the voltage applied to the gate very low.

Figure 1 shows an input protection circuit, in which a signal supplied to the input pad 11 is supplied via a diffused resistor R to the gate of the transistor Tr1 constituting the inner wAIg circuit.

Then, when a surge voltage is applied to input pad 1,
The Zener diode Ds formed by the diffused resistor R and the semiconductor substrate acts as a breakdown circuit, and the surge voltage is short-circuited, so that the gate of the transistor TrJ constituting the internal circuit is maintained.

Reference numeral 42m indicates an output conservation circuit, in which transistors TrJ and VhFiTrl forming the internal circuit are supplied with voltage from the connection point due to the non-transition and non-transmission states. The output signal thus obtained is supplied to the output pad 1z via the resistor R. When a surge voltage is applied to this output pad 12, the Zener diode DI enters a breakdown state, and the surge voltage is short-circuited.

Figure 3 is a cross-sectional diagram of the above-mentioned retarding circuit (Zener diode Dz and guarantee resistor R), and shows the structure of the P-circuit semiconductor substrate IS.
First, a P+ diffusion layer J4 is provided by ion implantation to increase the field inversion potential. Then, a silicon oxide film 15 is formed on this diffusion layer 14, and after buttering this silicon oxide film 15, an N 2 diffusion region 16 is formed. A vapor phase growth layer 11 of silicon oxide film is coated on the substrate thus formed! jI, and this vapor phase growth layer 11
After buttering, pad.

Aluminum 18 is vapor-deposited on wiring and the like.

Here, the diffusion layer thickness of the guarantee resistor RFiN and the Zener diode Dz are the expansion layer of N116 and the semi-substrate substrate 11.
14, each of them is divided into n squares.

However, in the maintenance circuit having such a structure, even if gate dielectric breakdown can be prevented, junction breakdown of the P-N junction of the protection diode cannot be sufficiently prevented, resulting in a drawback. That is, in the case of the diffusion layer I6 formed with a substantially uniform diffusion depth as shown in FIG. The withstand voltage of the portion 19 is low. Therefore, the overcurrent that occurs when the protection diode Dz breaks down when a high voltage is applied tends to concentrate on this portion 1g, which may cause the junction 9 near the contact portion to break down. Easy to invite -0 This invention was made in view of the above-mentioned circumstances, and its purpose is to alleviate the current concentration at the P-Ni 1 junction near the contact when an appropriate amount of input is applied, and to reduce the junction. 4; 1iLJ11 is prevented and the diffusion layer has a
It is an object of the present invention to provide a conductor integrated circuit device that can effectively utilize the characteristics.

Hereinafter, one embodiment of this invention will be described. I will clarify.

No 46! U(a) and (b) respectively show the structure, and U (a) and (b) are pattern plan views, and (b) - is a cross-sectional configuration diagram. That is, depletion transistors are arranged around 1m8 of the contact to form a high resistance region, and a P diffusion layer 14 is formed on the semiconductor substrate 13. After forming the silicon oxide film 15 and the N diffusion region 1tj1k1M,
A depletion transistor TrD having a polysilicon gate is formed in a =-shape so as to surround the contact portion CH between the N diffusion region 16 and the input pad 18 .

In the figure, Pa is the polysilicon gate of the transistor TrD, and c is the channel.Normally, a large area is required for a high resistance region, for example, in Figures 5(a) and (b).
), the transistor can be used as a high resistance region so that high resistance can be obtained in a small area by replacing the load resistor R2 in the figure -) by shorting the gate and drain of the transistor Tr4. .

46 (a)'' and (e) are respectively 0 for explaining the method of forming the depletion transistor TrD, that is, as shown in FIG. A silicon oxide film 15 is sequentially formed in region 14. Then, a silicon oxide film 20 which becomes a gate insulating layer of the transistor TrD is formed, a photoresist 21 is applied thereon, and this photoresist 21 is patterned. Furthermore, phosphorus (P''JJ) is formed through the opening of the photoresist 21 formed with the above-mentioned turns.
Alternatively, ion implantation is performed on the island (A island). This state (
b) As shown in the figure. Next, the photoresist 21 is removed and i
After forming the step, etching is performed to remove the silicon oxide film 20 at the ion-implanted portion leaving the gate insulating layer of the transistor TrD, as shown in FIG. 3(C).

Then, a polysilicon layer Po is placed on the substrate formed as described above, and a photoresist xzt- is applied and turned into a predetermined shape.
Next, a transistor TrD as shown in the figure (.) is constructed by expanding N2 to the parts that will become the source and drain of the transistor.

Thereafter, a vapor phase growth film 17 of a silicon oxide film, an aluminum pad, and a structure 18 are formed.

If a surge-like high voltage is applied to the *iδ circuit in this way, the area around the contact is in the above high resistance region i! l
Therefore, the overcurrent caused by diode breakdown is limited to 8 ns in this high resistance region, and it is possible to prevent overcurrent from concentrating on the P-N junction around the contact.

First, the potential is transmitted to the internal circuit via the diffusion layer, and the potential can be sufficiently lowered by this diffusion layer, and the inner itttm path can also be sufficiently maintained.

7th g! 1(a) and (b) are the above transistors TrD
Figure (a) is a pattern plan view, and figure (a) is a cross-sectional configuration diagram. That is, the transistor Tr
The gate insulating film 20 of D and the silicon oxide @1g are bonded to each other, and the polysilicon gate (polysilicon gate) P is formed.

is connected to the N+ diffusion ring on the contact side, and even in such a false fJ, it is possible to prevent excessive concentration of accents to the P -Niik around the Yuko contact and obtain the same effect as in the above embodiment. It will be done.

In the above embodiment, the input protection circuit has been described, but it goes without saying that it may be provided in the output protection circuit in the same manner.

As explained above, according to the present invention, contact jI
By arranging depletion temperature transistors around ii, it is possible to obtain a semiconductor closed-circuit product circuit device that can effectively prevent junction breakdown in the vicinity of the contacts, which is likely to occur due to overflow or current when over-relaxed pressure is applied.

[Brief explanation of drawings]

FIGS. 1 and 21 are diagrams respectively showing an input protection circuit and an output protection circuit in a conventional conductor integrated circuit device;
3 is a cross-sectional view showing an example of patterning of the storage diode and diffusion layer in the circuit shown in FIGS. 1 and 2, and FIGS. 4(a) and 4(b). -1 Semiconductor collection and Mj! each according to an embodiment of the present invention! Fig. 5 (a) shows the pattern plane of N (contact in the input/output protection circuit) and its cross section. (b) t:L circuit diagram for explaining the TEG occupied surface of the resistive element, Figure 6 (a) to (e) ld respectively Brain Figure 4-), Formation of the tip-pressure type transistor in (b) Diagram for explaining the method, tuna figure 7 (a),
(b) is a pattern plan view showing a modified configuration example of the above depression pear transistor and -[! [ ] It is a configuration diagram. TrD...High resistance region (depression type transistor), CH...Contact part. Applicant's agent Patent attorney Takehiko Suzue Figure 1
$2 v! J Figure 4jlIs Figure (a) (b) Figure 6

Claims (1)

[Claims] (1) Protect the input signal or output signal with a protective resistor.
The input voltage is outputted through the impurity diffusion layer that connects the diode, and the insulation layer 11 has a high resistance region around the impurity diffusion layer around the contact area between the impurity diffusion layer and the wiring.
A semiconductor integrated circuit device having a circuit configured as follows. (To) The semiconductor integrated circuit device O according to claim 1, wherein the high resistance region is formed by a depressed silicon transistor.