JPS6152988B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the structure of an integrated semiconductor device having a plurality of single crystal islands.

An example of the prior art is shown in FIGS. 1 and 2.

A polycrystalline substrate 1 made of silicon is surrounded by an insulating layer 2 made of silicon dioxide, for example ^.
An N-type single crystal island (substrate) 4 having a buried layer 3 is formed. Furthermore, an N ⁺ type conductive layer 5 and a P type conductive layer 6 are formed on the single crystal island 4.

Wiring metals 8 and 8' made of aluminum, for example, are applied to these conductive layers 5, 6 via an insulating layer 7 made of silicon dioxide, for example. The wiring metal passes over the island boundaries 10, 10', and the terminal ends 11, 11' of each wiring metal are located on the adjacent single crystal islands. Electrode portions 9, 9' made of, for example, lead and tin are provided at the end portions to enable electrical connection with external electrode terminals (not shown).

In a typical integrated semiconductor device, it is customary to position an electrode portion at the periphery of a semiconductor substrate in order to facilitate electrical connection with an external electrode terminal.
On the other hand, the position of each circuit element in an integrated semiconductor device is
Since the area of the semiconductor substrate is determined while considering various characteristics to minimize the area, the wiring metal that ultimately connects each circuit element and the electrode section will crawl between each single crystal island on the semiconductor substrate. It is customary.

Here, in FIGS. 1 and 2, attention is paid to the wiring metal 8' on the P-type conductive layer 6 side. Since this wiring metal 8' is applied so as to pass through the single crystal island 4 and the boundary 10 between the adjacent islands, it is affected by the potential of the wiring metal 8', and a depletion layer is formed under the wiring due to the MOS effect. It spreads, goes around the single crystal island bottom, forms a so-called channel, and exhibits an electrical short circuit phenomenon.

For this reason, it is customary to prevent the above-mentioned short circuit phenomenon by providing an N ⁺ buried layer 3 called a so-called channel cut in a part under the wiring. However, although we were able to prevent the depletion layer from expanding by using the N ⁺ buried layer 3 for channel cuts,
Electric field concentration occurs at the N ⁺ boundary 13 of the N ⁺ buried layer 3, and a new problem has arisen in that the withstand voltage cannot be increased above the voltage determined by the avalanche phenomenon.

Since the aforementioned electric field concentration depends on the electric field strength due to the potential difference between the wiring metal 8' and the single crystal island 4,
Care is taken to alleviate electric field concentration by increasing the thickness t of the insulating layer 7 on the N ⁺ buried layer 3 and to ensure the necessary withstand voltage. FIG. 5 shows the relationship between the insulating layer thickness t and the electric field strength at the N ⁺ boundary. From this figure, it can be seen that electric field concentration is alleviated by increasing the thickness t of the insulating layer.

However, silicon dioxide, silicon nitride, etc. are generally used as the insulating layer 7.
When these materials become thick, they exhibit a peeling phenomenon, and there is a practical limit to the thickness that can be formed. Normally, it is said that it is difficult to have a thickness of 4 μm or more.

Therefore, with conventional technology, it is not possible to sufficiently alleviate the electric field concentration at the N ⁺ boundary, and considering the variations in the thickness of the insulating layer during manufacturing, it is difficult to stably obtain an industrially sufficient withstand voltage. There was no way I could do that.

An object of the present invention is to provide an integrated semiconductor device having high breakdown voltage characteristics by preventing electric field concentration at the boundary of the channel cut N ⁺ buried layer under the metal wiring.

The present invention focuses on the fact that the presence of metal wiring on the N ⁺ buried layer for channel cut causes concentration of electric field in the channel cut portion, and in devices requiring high breakdown voltage characteristics, the buried layer for channel cut is By forming the terminal end of at least one metal wiring having an opposite conductivity type and connected to a conductive layer to which high voltage is to be applied in the same island as the element, the channel cut part, that is, the single crystal This prevents them from crossing the island boundary.

An embodiment of the present invention is shown in FIGS. 3 and 4.
In this example, since the single crystal island 4 and the N ⁺ buried layer 3, which is a channel cut, are N-type conductive layers, the terminal end of the metal wiring 8' connected to the P-type conductive layer 6, which is the opposite conductivity type. 11' is located within the single crystal island 4. On this terminal part 11',
For example, a solder ball electrode part 9' made of lead and tin is formed, and the so-called CCB (Controlled-Collapse-
It is connected to an external electrode terminal (not shown) using a bonding technique.

In FIGS. 3 and 4, the N ⁺ layer 5 has the same conductivity type as the N ⁺ buried layer 3, so even if the metal wiring 8 connected thereto crosses the N ⁺ buried layer 3 and the island boundary 10, , no electric field concentration occurs at the N ⁺ boundary and does not cause a drop in breakdown voltage. Therefore, in this embodiment, the insulating portion of the metal wiring 8 is extended to the adjacent island, as in the conventional case.

Furthermore, even if the region within the island to which the metal wiring is connected is of the opposite conductivity type to the buried layer, if the potential difference between the buried layer and the region is small, the electric field strength at the boundary of the buried layer is not significant. Since the metal wiring does not become large and the improvement in breakdown voltage is not inhibited, there is no problem even if the metal wiring crosses the channel cut portion, that is, the single crystal island boundary. According to experiments conducted by the inventors, the potential difference between the metal wiring and the base layer of the single crystal island is approximately 50V.
In this case, electric field concentration at the boundary of the buried layer becomes significant, and a countermeasure according to the present invention is required.

By implementing the present invention, the electric field strength at the N ⁺ boundary 13 is approximately 1 KV/cm as shown by the dotted line in FIG.
or less.

As for the electric wire section provided at the end of the metal wiring 8', instead of the lead-tin solder ball electrode shown and explained earlier, it is also possible to use a thin wire made of aluminum or gold to connect to the external electrode terminal. It is.

FIG. 6 shows a comparison between the breakdown voltage of an integrated semiconductor device obtained by the conventional example and that according to the present invention when the thickness of the insulating layer 7 is 3.5 μm. The bar graphs with white background are based on the conventional example, and the bar graphs with diagonal lines are based on the present invention. As is clear from this figure, in the conventional example, only about 400V of withstand voltage could be obtained, but according to the present invention, about 500V can be obtained.
An improvement in voltage resistance of approximately 25% has been achieved. Also,
It was confirmed that the withstand voltage when implementing the present invention is hardly affected by the thickness of the insulating layer.

As described in detail above, according to the present invention, a semiconductor device having stable high breakdown voltage characteristics can be obtained regardless of fluctuations in the thickness of the insulating layer due to variations in the manufacturing process.

[Brief explanation of the drawing]

FIG. 1 is a plan view showing a conventional example of an integrated semiconductor device, FIG. 2 is a sectional view taken along line A-A' in FIG. The figure is a cross-sectional view taken along line A-A' in Figure 3, Figure 5 is a diagram showing the relationship between the thickness of the insulating layer and electric field strength, and Figure 6 is a diagram showing an example of breakdown voltage distribution in semiconductor devices according to the conventional example and the present invention. It is a distribution map. 1... Polycrystalline substrate, 2... Insulating layer, 3... N ⁺
Buried layer, 4... Single crystal island, 7... Insulating layer, 8,
8'...metal wiring, 9,9'...electrode part, 10,1
0'...Island boundary, 11,11'...Terminal part, 12...
...Semiconductor substrate, 13...N ⁺ boundary.

Claims (1)

[Claims] 1. A plurality of semiconductor single crystal islands each having a predetermined PN junction therein are electrically isolated from each other by an insulating layer and formed on the same substrate, and
In an integrated semiconductor device in which a high concentration region of the same conductivity type as the base of the semiconductor single crystal island is formed along the inside of the insulating layer, a high concentration region of the opposite conductivity type from the base within a certain semiconductor single crystal island An integrated semiconductor device characterized in that a metal wiring connected to at least one region is configured such that the metal wiring does not cross the boundary of the island but has its terminal end within the island.