JPS5867041A - Semicondutor integrated circuit - Google Patents

Abstract

PURPOSE:To improve a high-frequency characteristic by forming an isolation region surrounding an element region while being divided into plural sections, mutually contacting depletion layers generated when reverse bias voltage is applied and using the layers as one parts of insulating isolation regions. CONSTITUTION:The isolation regions 5 formed so as to surround a plurality of the element regions 1 are shaped while being divided into plural sections, the depletion layers 4 are generated from each siolation region 5 by applying reverse bias voltage among separate isolation region 5 and the element regions 1, and the layers 4 expand to the circumference in response to the increase of reverse bias voltage, thus mutually contacting the layers. Respective element region 1 is mutually isolated completely and electrically by the depletion layer 4 and the isolation regions 5 under the state, and brought to an isolated state. According to such constitution, when the intervals of the isolation regions are properly selected previously in response to the purpose, use, etc., divided into plural sections and formed, the areas of the isolation regions are decreased, and capacitance by the depletion layers can be reduced remarkably.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit configured to use a depletion layer generated from a PN junction as part of an insulating isolation region.

2. Description of the Related Art In semiconductor integrated circuits, a PN junction is widely used as an isolation region for separating element regions from each other.

Figures 1 and 2 show such P
In the cross-sectional view and top view showing the N-junction isolation structure, l is an element region (island region) consisting of a first conductivity type semiconductor region (for example, N type) in which a desired circuit element is to be formed, and 2 is an element region that separates the element region 1. An isolation region 3 consisting of a second conductivity type semiconductor region (for example, P type) is a PN junction formed between the regions 1 and 2.

In the above, by connecting the lowest potential of the circuit to the isolation region 2, the PN junction 3 is reverse biased, so that almost no current flows through the PN junction 3, so it has a high resistance similar to an insulator. Therefore, each element region l is electrically isolated from each other.

However, in this PN junction isolation structure, a depletion layer 4 is inevitably generated from the PN junction 3 due to reverse bias, and the capacitance due to this depletion layer 4 is added between each element region l and the lowest potential, so that high frequency A drawback arises that deteriorates the characteristics.

The present invention has been made in order to solve the above problem, and is made by dividing an isolation region surrounding an element region into a plurality of parts to form a depletion layer that is generated when a reverse bias voltage is applied to these plurality of isolation regions. It is an object of the present invention to provide a semiconductor integrated circuit constructed in such a manner that the conventional drawbacks can be eliminated by making the depletion layers contact each other and using the depletion layers as part of an insulating isolation region. Embodiments of the present invention will be described below with reference to the drawings. .

FIG. 3 is a top view showing a semiconductor integrated circuit according to an embodiment of the present invention. Reference numeral 5 denotes a separation region formed so as to surround a plurality of bare hand regions, which are divided into a plurality of regions.

By applying a reverse bias voltage between each isolation region 5 and the element region 1, a depletion layer 4 is generated from each isolation region 5 and spreads to the surrounding area as the reverse bias voltage increases, so that they come into contact with each other. Become. In this state, each element region 1 is completely electrically isolated from each other by the depletion layer 4 and the isolation region 5, 2, so-called isolating, and therefore, according to the structure of the present invention as described above. For example, since the area of the isolation region can be reduced, the capacitance due to the depletion layer can be much reduced compared to the conventional structure. Therefore, high frequency characteristics can be improved, and at the same time, size reduction can be achieved by reducing the area of the separation region, thereby making it possible to reduce costs.

Furthermore, as described above, it becomes possible to integrate what was conventionally constructed from individual parts, thereby improving reliability.

[Brief explanation of the drawing]

1 and 2 are both a sectional view and a top view showing a conventional example, and FIG. 3 is a top view showing an embodiment of the present invention. 1...Element region, 3...PN junction, 4...Depletion layer, 5...Isolation region. Figures 1-2 Figure 3 Roro' Rorororororo Ward

Claims (1)

[Claims] (1) A semiconductor integrated circuit characterized in that a plurality of element regions are separated by a depletion layer (4). 2. A plurality of device regions comprising a first conductivity type semiconductor region are surrounded by a plurality of second conductivity type semiconductor regions.1.
2. The semiconductor integrated circuit according to claim 1, wherein the depletion layer is generated by applying a reverse insulating pressure to the second conductivity type semiconductor region.