JPS6153756A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reduce parasitic capacitance between bonding pad and P type substrate by forming P type diffused layer at the N type semiconductor surface just under the bonding pad in view of connecting in series the junction capacitances by the P type diffused layer. CONSTITUTION:Dielectric capacitance C of insulating film 4, junction capacitance C3 between P type diffused layer 8 and N type layer 2 and junction capacitance between N type layer 2 and P type substrate 1 are connected in series between the bonding pad and P type substrate and parasitic capacitance CI can be related by the formula 1. Here, the parasitic capacitance CII of the existing case where there is no capacitance C3 is related by the formula 2. From such relatrelations, a relation 1/CII>1/CI can be obtained. Therefore, a parasitic capacitance can be made smaller by inserting a P type diffused layer 8 under the bonding pad.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to countermeasures against parasitic capacitance under bonding pads of semiconductor devices.

[Background technology]

FIG. 4 is a sectional view showing the structure of a bonding pad portion in an IC studied by the inventor before the present invention. As shown in FIG. 4, an n-type silicon layer 2 is formed on a P-type silicon crystal substrate 1 by epitaxial growth Q, and the surface of this n-type silicon layer 2 is covered with an isolation layer 3 made of a P-type layer. Accordingly, it has a structure in which it is electrically divided into several semiconductor regions, and elements (not shown) such as transistors are formed on the surface of the separated semiconductor regions. These aluminum terminals (wirings) connected to (;3T-) are connected to external leads by bonding wires 6 as bonding pads 5 around the chip (substrate). Pad 5 is 5i, which is a glossy B film on the surface of silicon layer 2.
For example, if there is a pinhole (microhole) in 5i02 directly below the pad, a leakage current will flow from the pinhole to the semiconductor layer 2, which may have an unfavorable effect on the operation of the circuits constituting the IC. give. In order to prevent such current leakage, as shown in FIG. 4, an isolation layer 3 consisting of a p-type layer is provided directly under the peripheral part of the butt, and the n-type layer 2 directly under the bonding pad is floating (electrically It is a floating island). This technique is disclosed in Japanese Patent Publication No. 46-25466.

As shown in FIG. 4, a capacitance is generated between the conductor of the bonding pad and the half pad m. and n-type semi-c body layer 2
There is also a junction capacitance C2 between and the P-type semiconductor substrate 1,
A P-type substrate 1 is connected to ground, which is the lowest operating potential, through an isolation P-type layer 3.

In this case, a parasitic capacitance C is generated by connecting CI and C2 in series, as shown in the equivalent circuit diagram of FIG.

If the bonding pad 5 is an input terminal and the SiO□ film 4 under the pad is extremely thin, such as when it is formed in a step near the final step in the IC'Il fabrication process, the parasitic capacitance C becomes large.

When C becomes large, the time constant becomes large due to the equivalent impedance of the wiring in the circuit, and the signal delay increases. This becomes a problem especially in ICs that process high-frequency minute signals. The above matters were clarified by the inventor.

[Purpose of the invention]

The present invention has been made in view of the above-mentioned problems, and its purpose is to reduce parasitic capacitance in bonding pads.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

That is, in a semiconductor device in which an n-type semiconductor layer is formed on a p-type semiconductor substrate and has a bonding pad on an insulating film on the surface of the n-type semiconductor m, a p-type diffusion layer is formed on the surface of the n-type semiconductor layer directly under the bonding pad. The parasitic capacitance between the bonding pad and the p-type substrate is
This reduces the west junction capacitance due to the type diffusion layer by connecting it in series, thereby reducing the delay speed.

〔Example〕

FIG. 1 shows an embodiment of the present invention, in which i17? of a portion near a bonding pad in a semiconductor device is shown. It is a front view. FIG. 2 is a circuit diagram equivalent to FIG. 1.

1 is a P-type silicon substrate, 2 is an n-type silicon layer epitaxially grown on the substrate 1, 7 is an isolation U-shaped groove with a 5i02 film 4 formed on the inner surface of the groove, and polysilicon 9, etc. inside the groove. is filled. Note that instead of such an isolation groove, an isolation P-type layer 3 as shown in FIG. 4, an isoplanar oxide film, or the like may be used.

Reference numeral 5 denotes an aluminum film serving as a bonding pad, onto which a gold wire 6 is wire-bonded.

8 is a P-type diffusion layer formed on the surface of the n-type layer 2 directly under this bonding butt. This P-type diffusion layer 8 has a P-type base of an npn transistor, a P-type injector such as FIL (Injection Stacking Logic), and a P-type base in another area separated by the isolation part of the half-core body 1. It is diffused in the same process as forming it.

〔effect〕

In such a semi-group device, the dielectric capacitance c1. The junction capacitance C3 between the p-type diffusion layer 8 and the n-type layer 2, and the junction capacitance between the n-type layer 2 and the p-type substrate 1 are connected in series as shown in FIG. Create a parasitic capacitance C□ with the value of (1).

1/CI = 1/Ct +l/C3 = 1/C2...
...It appears as (1).

Incidentally, the parasitic capacitance CIX in the case of the conventional Kizou (FIG. 4) without C3 is as follows.

Comparing (1) and (2), in (1), due to the extra C3, 1/Cn>1/CI, and therefore Cn<Cr.

Therefore, according to the present invention, by inserting the P type diffusion layer 8 under the bonding pad, it is possible to reduce the parasitic capacitance.

Part 3 shows a plan view of an example of an IC that uses a groove structure in which a P-type diffusion layer is placed under the pad.
In the chip, a voltage follower 9 is connected to a bonding pad serving as an input terminal (IN).

The present invention is particularly effective when the 5i02 film on which the bonding pad is formed is of low quality (for example, 3000A or less).

By reducing the parasitic capacitance under the pad as described below, it is possible to implement an IC system that processes high-frequency, minute signals with high performance.

〔Scope of application〕

The present invention is applicable to general semiconductor devices such as ICs and LISs.

The present invention is particularly effective when applied to ICs that require high-frequency minute signal processing.

[Brief explanation of drawings]

FIG. 1 is a sectional view of a main part of a semiconductor device showing an embodiment of the present invention. FIG. 2 is a circuit diagram equivalent to FIG. 1. FIG. 3 is a partial plan view of a semiconductor chip to which the device of FIG. 1 is applied. FIG. 4 is a sectional view showing an example of a semiconductor device having bonding pads.6 FIG. 5 is a circuit diagram equivalent to FIG. 4. 1... P-type semiconductor substrate, 2... Epitaxial n-type semiconductor layer, 3 - Isolation p-type layer, 4 Surface oxide film, 5... Aluminum film (bonding pad, 6
... wire, 7 ... isolation groove, 8 ... p
type diffusion layer, 9--polysilicon layer, 10--voltage follower, Ql...NPNI-transistor, No.
1 Figure 2 Figure 3

Claims (1)

[Claims] 1. A second conductivity type semiconductor layer having a conductivity type opposite to that of the base body is formed on one main surface of a first conductivity type semiconductor substrate, and the surface of the second conductivity type semiconductor layer is covered with an insulating film. , a semiconductor device in which a conductor film at the end of the wiring serving as a bonding pad is formed on the insulating film, a first conductivity type diffusion layer is formed on the surface of the second conductivity type semiconductor layer directly under the conductor film; A semiconductor device comprising a plurality of series capacitances including a junction capacitance between the first conductivity type diffusion layer and the second conductivity type semiconductor layer between the bonding pad and the base. 2. The semiconductor device according to claim 1, wherein the second conductivity type semiconductor layer in which the first conductivity type diffusion layer is formed is electrically isolated from other second conductivity type semiconductor layers surrounding it. .