JPS6222454B2 - - Google Patents
Info
- Publication number
- JPS6222454B2 JPS6222454B2 JP54103998A JP10399879A JPS6222454B2 JP S6222454 B2 JPS6222454 B2 JP S6222454B2 JP 54103998 A JP54103998 A JP 54103998A JP 10399879 A JP10399879 A JP 10399879A JP S6222454 B2 JPS6222454 B2 JP S6222454B2
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- layer
- insulating film
- junction
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000010410 layer Substances 0.000 claims description 24
- 239000004065 semiconductor Substances 0.000 claims description 12
- 239000000758 substrate Substances 0.000 claims description 5
- 239000011229 interlayer Substances 0.000 claims description 4
- 238000009792 diffusion process Methods 0.000 description 8
- 230000003071 parasitic effect Effects 0.000 description 5
- 229920001721 polyimide Polymers 0.000 description 4
- 239000004642 Polyimide Substances 0.000 description 3
- 238000000605 extraction Methods 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【発明の詳細な説明】
この発明は多層配線を有する半導体装置におけ
る寄生MOSトランジスタ防止技術に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a technique for preventing parasitic MOS transistors in a semiconductor device having multilayer wiring.
モノリシツクIC（半導体集積回路）におい
て、半導体基板と表面酸化膜及びその上のAl
（アルミニウム）配線とによつて生じる寄生MOS
トランジスタの防止あるいはチヤージこぼれによ
る寄生MOSトランジスタの防止のために従来よ
り、n+拡散によるチヤネルストツパを通常Al配
線からなるゲート部分の下に設け、p-反転層を
分離する方法が採られている。また高電位のAl
配線によりp-反転を防止することも考えられて
いるが全てのpn接合表面部をAl配線のみでカバ
ーすることはできないため、一部にn+拡散層を
併用する必要があり、いずれにしてもn+拡散層
形成のためにチツプ面積が拡大するという問題を
避けられなかつた。 In a monolithic IC (semiconductor integrated circuit), the semiconductor substrate, surface oxide film, and Al
Parasitic MOS caused by (aluminum) wiring
In order to prevent transistors or parasitic MOS transistors due to charge spillage, a conventional method has been adopted in which a channel stopper made of n + diffusion is provided under the gate portion, which is usually made of Al wiring, to separate the p - inversion layer. Also, high potential Al
It has been considered to prevent p - inversion by wiring, but since it is not possible to cover all the p-n junction surface area with Al wiring alone, it is necessary to use an n + diffusion layer in some areas. However, the problem of expanding the chip area due to the formation of the n + diffusion layer was unavoidable.
本発明は上記した従来技術の問題点を解消する
べくなされたものであり、その目的はチツプ面積
を増加することなく寄生MOSトランジスタを防
止できる半導体集積回路装置の提供にある。 The present invention has been made to solve the problems of the prior art described above, and its purpose is to provide a semiconductor integrated circuit device that can prevent parasitic MOS transistors without increasing the chip area.
上記目的を達成するためこの発明は、多層配線
を有する半導体装置であつて、第１層配線と第２
層配線とで一部をオーバラツプさせて少なくとも
pn接合表面部の上を覆うとともに表面絶縁膜に
よるしきい値電圧以上の高電位を上記配線に印加
することを特徴とする。 In order to achieve the above object, the present invention provides a semiconductor device having multilayer wiring, wherein a first layer wiring and a second layer wiring.
At least partially overlap the layer wiring.
It is characterized in that it covers the pn junction surface portion and applies a high potential higher than the threshold voltage due to the surface insulating film to the wiring.
第１図及び第２図は本発明をnpnトランジスタ
の多層配線構造に適用した場合の一例を示す。 FIGS. 1 and 2 show an example in which the present invention is applied to a multilayer wiring structure of an npn transistor.
同図において１はn-Si基板又はn-エピタキシ
ヤル層、２はp+拡散ベース、３はn+拡散エミツ
タ、４はn-拡散コレクタ取出し部である。５は
表面絶縁膜であるSiO2膜、６，７，８は上記エ
ミツタ、ベース及びコレクタ取出し部にコンタク
トし絶縁膜上に延在する第１層Al配線、９は層
間絶縁膜となるポリイミド系樹脂膜（例えばポリ
イミドイソインドロキナゾリンジオン）、１０は
スルーホール、１１は第２層Al配線でスルーホ
ールを通じて第１層Al配線に接続する。上記第
２層Al配線は第２図の太実線で示すように少な
くともベース接合、エミツタ接合の表面部を第１
層Al配線にオーバーラツプして覆うように形成
され、この第２層Al配線には絶縁膜５，９にか
かわるシキイ値電圧Ｖthよりも少なくとも高い電
位、例えばＶC：50V，Ｖth：10VとしてＶ≧ＶC
−Ｖthすなわち40V以上の電位をかけるようにす
る。 In the figure, 1 is an n - Si substrate or an n - epitaxial layer, 2 is a p + diffusion base, 3 is an n + diffusion emitter, and 4 is an n - diffusion collector extraction part. 5 is a SiO 2 film which is a surface insulating film; 6, 7, and 8 are first layer Al wirings that contact the emitter, base and collector extraction portions and extend on the insulating film; 9 is a polyimide-based interlayer insulating film. A resin film (for example, polyimide isoindoquinazoline dione), 10 is a through hole, and 11 is a second layer Al wiring, which is connected to the first layer Al wiring through the through hole. As shown by the thick solid line in Figure 2, the second layer Al wiring has at least the base junction and emitter junction surface areas connected to the first layer.
The second layer Al wiring is formed to overlap and cover the layer Al wiring, and the second layer Al wiring is provided with a potential that is at least higher than the threshold voltage V th related to the insulating films 5 and 9, for example, V C : 50V, V th : 10V. V≧V C
-V th, that is, apply a potential of 40V or more.
以上実施例で述べた本発明によれば、少なくと
もpn接合上では絶縁膜を介してAl配線が一部で
はオーバーラツプされてすきまなく形成され、こ
れに対しＶthより高い電位が与えられていること
により、絶縁膜下に生じるであろう寄生MOSト
ランジスタによるp-反転１２を防止することが
できる。このようなAl配線のみによるp-反転防
止を可能としたことにより、n+拡散層によるチ
ヤネルストツパが不要となり、チツプ面積を増大
させることなく集積化を実現できる。なお層間絶
縁膜として高耐熱性の有機絶縁膜であるポリイミ
ド系樹脂膜（例えばポリイミドイソインドロキナ
ゾリンジオン）を使用することにより、容量の増
大をなくし、そのち密性により配線間短絡をなく
し、又その表面平坦化性により上層のAl配線の
断線を防止し得る。したがつて本発明は大出力の
半導体装置、例えばパワーICやリニアIC又は
MOSIC等に適用してきわめて有効である。 According to the present invention described in the embodiments above, at least on the p-n junction, the Al wiring is partially overlapped through the insulating film and formed without any gap, and a potential higher than V th is applied to the Al wiring. This makes it possible to prevent p - inversion 12 caused by a parasitic MOS transistor that would otherwise occur under the insulating film. By making it possible to prevent p - inversion using only Al wiring, a channel stopper using an n + diffusion layer is no longer necessary, and integration can be achieved without increasing the chip area. Note that by using a polyimide resin film (for example, polyimide isoindoquinazolinedione), which is a highly heat-resistant organic insulating film, as the interlayer insulating film, an increase in capacitance is eliminated, and its tightness eliminates short circuits between wirings. Due to its surface flattening properties, disconnection of the upper layer Al wiring can be prevented. Therefore, the present invention is applicable to high-output semiconductor devices such as power ICs, linear ICs,
It is extremely effective when applied to MOSIC, etc.
本発明は前記実施例に限定されない。第２層の
Al配線の平面形状は設計上の必要に応じて種々
変更できる。 The invention is not limited to the above embodiments. 2nd layer
The planar shape of the Al wiring can be changed in various ways depending on design needs.
第１図は本発明による半導体装置の一実施例の
断面図、第２図は同平面図である。
１……Si基板、２……p+拡散ベース、３……
n+拡散エミツタ、４……n+拡散コレクタ取出
部、５……表面絶縁膜、６，７，８……第１層
Al配線、９……層間絶縁膜、１０……スルーホ
ール、１１……第２層Al配線、１２……p-反
転。
FIG. 1 is a sectional view of an embodiment of a semiconductor device according to the present invention, and FIG. 2 is a plan view thereof. 1...Si substrate, 2...p + diffusion base, 3...
n + diffused emitter, 4... n + diffused collector extraction part, 5... surface insulating film, 6, 7, 8... first layer
Al wiring, 9... interlayer insulating film, 10... through hole, 11... second layer Al wiring, 12... p - inversion.
Claims (1)
接合を構成する第１、第２半導体領域と、その第
１半導体領域にコンタクトし、そのPN接合を絶
縁膜を介して横切る第１層目配線と、そのPN接
合を覆うように層間絶縁膜を介して上記第１層目
配線上に形成された半導体基体表面反転防止の所
定電位が与えられる第２層目配線とからなること
を特徴とする多層配線半導体装置。1 PN whose end terminates on the surface of the semiconductor substrate
First and second semiconductor regions constituting a junction, a first layer wiring that contacts the first semiconductor region and crosses the PN junction via an insulating film, and an interlayer insulating film that covers the PN junction. A multilayer interconnection semiconductor device comprising: a second layer interconnection formed on the first layer interconnection to which a predetermined potential for preventing surface inversion of the semiconductor substrate formed on the first layer interconnection is applied.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10399879A JPS5627945A (en) | 1979-08-17 | 1979-08-17 | Semiconductor device with multilayered wiring |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10399879A JPS5627945A (en) | 1979-08-17 | 1979-08-17 | Semiconductor device with multilayered wiring |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5627945A JPS5627945A (en) | 1981-03-18 |
| JPS6222454B2 true JPS6222454B2 (en) | 1987-05-18 |
Family
ID=14368954
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10399879A Granted JPS5627945A (en) | 1979-08-17 | 1979-08-17 | Semiconductor device with multilayered wiring |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5627945A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63253649A (en) * | 1987-04-10 | 1988-10-20 | Nec Corp | Semiconductor device |
-
1979
- 1979-08-17 JP JP10399879A patent/JPS5627945A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5627945A (en) | 1981-03-18 |
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