JPS61137360A - Complementary mos integrated circuit device - Google Patents
Complementary mos integrated circuit deviceInfo
- Publication number
- JPS61137360A JPS61137360A JP59260362A JP26036284A JPS61137360A JP S61137360 A JPS61137360 A JP S61137360A JP 59260362 A JP59260362 A JP 59260362A JP 26036284 A JP26036284 A JP 26036284A JP S61137360 A JPS61137360 A JP S61137360A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- wirings
- region
- film
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000000295 complement effect Effects 0.000 title claims description 8
- 239000000758 substrate Substances 0.000 claims abstract description 33
- 239000004065 semiconductor Substances 0.000 claims abstract description 6
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 5
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 4
- 230000001590 oxidative effect Effects 0.000 abstract description 2
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 abstract description 2
- 229910021342 tungsten silicide Inorganic materials 0.000 abstract description 2
- 150000002500 ions Chemical class 0.000 abstract 2
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 230000002093 peripheral effect Effects 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 239000002344 surface layer Substances 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 238000009792 diffusion process Methods 0.000 description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 150000004767 nitrides Chemical class 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- NBJBFKVCPBJQMR-APKOLTMOSA-N nff 1 Chemical compound C([C@H](NC(=O)[C@H](CCC(N)=O)NC(=O)[C@H](CCC(N)=O)NC(=O)[C@@H]1CCCN1C(=O)[C@H](CCCCN)NC(=O)[C@@H]1CCCN1C(=O)CC=1C2=CC=C(C=C2OC(=O)C=1)OC)C(=O)N[C@@H](CC=1C=CC=CC=1)C(=O)NCC(=O)N[C@@H](CC(C)C)C(=O)N[C@@H](CCCCNC=1C(=CC(=CC=1)[N+]([O-])=O)[N+]([O-])=O)C(=O)NCC(O)=O)C1=CC=CC=C1 NBJBFKVCPBJQMR-APKOLTMOSA-N 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0921—Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は相補型ＭＯＳ集積回路装置（ＣＭＯＳＴＣに係
り、ラッチアップ耐圧強化構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a complementary MOS integrated circuit device (CMOSTC), and relates to a latch-up voltage enhanced structure.
近年微細化が進むにつれて、０Ｍ０８１Ｃではラッチア
ップ現象が、大きな問題となってきている。As miniaturization progresses in recent years, the latch-up phenomenon has become a major problem in 0M081C.
ラッチアップ耐圧強化の九めには、高濃度エピタキシャ
ル基板を使用することにより基板抵抗を下げることが有
効であるが、Ｐチャンネル・トランジスタ領域とＮチャ
ンネル・トランジスタ領域との距離を小さくするだけで
は効果がなく、ＰＮ境界領域近くのウェル表面、を九は
基板表面で、ウェル電位ま几は基板電位をとる九めの電
極を形成することが必要である。従来、この電極はソー
スドレインと同時に形成される拡散層配線により、作ら
れてい九〇シかしこの構造では、配線抵抗が大きく、ラ
ッチアップに対して、十分な効果がなかつ次。また、こ
の拡散層をソース・ドレインと同時に形成する九め、現
在主流となっているシリコン・ゲー１−Ｍ０８ＩＣでは
、ゲート電極となるポリシリコン配線が、ウェルま九は
基板の電位をおきえる拡散１配線の上を通ることができ
ず、Ｐチャンネル・トラ７ジスタのゲート電極と、Ｎチ
ヤンネル・トランジスタのゲート電極とを直接結ぶこと
ができず、レイアウト上不都合であった。Ninth, it is effective to lower the substrate resistance by using a highly doped epitaxial substrate to strengthen the latch-up breakdown voltage, but it is not effective just to reduce the distance between the P-channel transistor region and the N-channel transistor region. It is necessary to form a ninth electrode that takes the well potential near the PN boundary region and the substrate surface, and the well potential or the substrate potential. Conventionally, this electrode was formed using a diffusion layer wiring formed at the same time as the source and drain, but this structure had high wiring resistance and was not sufficiently effective against latch-up. In addition, this diffusion layer is formed at the same time as the source and drain, and in the currently mainstream silicon gate 1-M08 IC, the polysilicon wiring that becomes the gate electrode is formed as a well layer, and the well layer is a diffusion layer that holds the potential of the substrate. The gate electrode of the P-channel transistor cannot be directly connected to the gate electrode of the N-channel transistor, which is inconvenient in terms of layout.
本発明の目的は、ウェルま７ｔ＋は基板の電位をおさえ
るための電極配線の抵抗を小さくシ、かつこの配線の上
にもゲート電極を形成するポリシリコノなどの配線が通
れるようにして、ラッチアップ耐圧を強化し、かつレイ
アウト上の無駄をなくし、チップの縮小化を計っｔ相補
型ＭＯＳ集積回路装置を提供することにある。The purpose of the present invention is to reduce the resistance of the electrode wiring for suppressing the potential of the substrate in the well 7t+, and also to allow the wiring such as polysilicon to form the gate electrode to pass over this wiring, thereby reducing the latch-up withstand voltage. It is an object of the present invention to provide a complementary MOS integrated circuit device which is designed to strengthen the circuit, eliminate waste in layout, and reduce the size of the chip.
本発明の構成は、第１導電型の半導体基板とその表面に
形成された第２導電型のウェルとからなる相補型ＭＯＳ
集積回路装置において、その表面のＰＮ境界領域近傍に
前記ウェルまたは基板電位をとる几めのシリサイドま九
はポリサイドからなる電極配線を走らせ、特にその上に
ゲート電極配線を通し九ことを特徴とする。The structure of the present invention is a complementary MOS comprising a semiconductor substrate of a first conductivity type and a well of a second conductivity type formed on the surface of the semiconductor substrate.
In the integrated circuit device, an electrode wiring made of polycide is run over the well or substrate potential near the PN boundary region on the surface of the integrated circuit device, and in particular, a gate electrode wiring is passed over the silicide layer. .
次に図面を参照しながら本発明の詳細な説明する。第１
図（ａｌｌｄ本発明の実施例の半導体基板の平面図、第
１図（ｂｌは第１図（ａ）の八−Ａ′線に沿って切断し
た断面図である。同図において、本実施例は、便宜上Ｎ
型基板にＰ型ウェルを形成した０ＭＯＳＩＣで、ＰＮ境
界近くのＮ型基板表面に、基板電位を形成するシリサイ
ド配線を形成するものとする。まず、Ｎｆｆ１半導体基
板１の表面にＰ型りエル２を形成し、窒化膜をマスクと
する通常のＬＯＧＯ８工程で、フィールド酸化膜９とゲ
ート酸化膜１０とを形成する。ゲート酸化膜１０の上に
マスク窒化膜を残した状態で、基板電位をとるためコン
タクト孔４ｔ−開孔し、その上にタングステン・シリサ
イド配線５ｔ−形成する。前記配線５にす／ｌ−イオノ
注入でドーグし、同時にＮ型拡散層３を形成する。次に
前記配＃ｉ１５を酸化性雰囲気で熱酸化し、配線表面に
シリコン酸化膜を形成する。Next, the present invention will be described in detail with reference to the drawings. 1st
Figure (alld) is a plan view of a semiconductor substrate according to an embodiment of the present invention. is N for convenience.
It is assumed that this is an OMOSIC in which a P-type well is formed on a type substrate, and a silicide wiring for forming a substrate potential is formed on the surface of the N-type substrate near the PN boundary. First, a P-type trench 2 is formed on the surface of the Nff1 semiconductor substrate 1, and a field oxide film 9 and a gate oxide film 10 are formed in a normal LOGO8 process using a nitride film as a mask. With the mask nitride film remaining on the gate oxide film 10, a contact hole 4t is opened to obtain a substrate potential, and a tungsten silicide wiring 5t is formed thereon. The wiring 5 is doped with S/l- ion implantation, and at the same time an N-type diffusion layer 3 is formed. Next, the wiring #i15 is thermally oxidized in an oxidizing atmosphere to form a silicon oxide film on the wiring surface.
次に、マスクの窒化膜を除去し、ゲートポリ７リコノ電
極６を形成する。この後は通常のシリコンゲートＣＭＯ
Ｓ工程で、０ＭＯＳＩＣｔ−形成する。Next, the nitride film of the mask is removed, and the gate polygon electrode 6 is formed. After this, normal silicon gate CMO
In step S, 0MOSICt- is formed.
本実施例によれば、Ｐチャンネル・トランジスタ領域と
Ｎチャ／ネル・トラ７ジスタ領域との関のＮ型基板表面
に、低抵抗の基板電極配線が形成され、ラッチアップ防
止に大きな効果を発揮するまた、ゲート・ポリシリコン
電極６配線が、基板電極配線の上を走り、レイアウト上
の自由度が大きく、基板電極をとるためのＮ型拡散層３
がソース・ドレイノ拡散層とは別に形成されるので、ソ
ース・ドシイノ領域との目合せマージンが最小にでき、
テップの縮小化にも役立つ。According to this embodiment, a low-resistance substrate electrode wiring is formed on the surface of the N-type substrate between the P-channel transistor region and the N-channel transistor region, which is highly effective in preventing latch-up. In addition, the gate polysilicon electrode 6 wiring runs over the substrate electrode wiring, giving a large degree of freedom in layout, and the N-type diffusion layer 3 for taking the substrate electrode.
is formed separately from the source/drain diffusion layer, so the alignment margin with the source/drain region can be minimized.
It is also useful for reducing the size of the step.
本発明としては、本実施例以外多くの構造が考えらｎる
。基板電極配線だけでなく、ウェル電極配線も同様に冥
現できる。両者を同時に形成することもまた有効である
。Many structures other than this embodiment are conceivable for the present invention. Not only substrate electrode wiring but also well electrode wiring can be realized in the same way. It is also effective to form both at the same time.
以上説明したように、本発明によれば、ウェルまたは基
板電極配線がシリサイド、またはポリサイドからなるた
め、従来の拡散層配線と比べ、抵抗が１桁以上下がり、
ラッチアップ耐量が約１０倍大きくなり、またウェル、
または基板電極配線の上を、ゲート・ポリシリコン電極
配線を走らすことができるので、レイアウト上の自由度
が太きくなり、テップの縮小にも役立つという効果が得
られる。As explained above, according to the present invention, since the well or substrate electrode wiring is made of silicide or polycide, the resistance is reduced by more than one order of magnitude compared to conventional diffusion layer wiring.
The latch-up resistance is approximately 10 times greater, and the well and
Alternatively, since the gate/polysilicon electrode wiring can be run over the substrate electrode wiring, the degree of freedom in terms of layout is increased and the effect of helping to reduce the step size can be obtained.
第１図（ａ）は本発明の実施例の相補型ＭＯＳ集積回路
装置を示す平面図、第１図（ｂ）は第１図（ａ）の八−
Ａ′線に沿って切断して見た断面図である。
同図において、ｌ・・・・・・Ｎ型シリコ／基板、２・
・・・・・Ｐ型ウェル、３・・・・・・Ｎ型拡散層、４
・・・・・・基板電極用コンタクト、５・・・・・・タ
ングステン・クリサイド基板電極配線、６・・・・・・
ポリシリコン・ゲート電極配線、７・・・・・・Ｐチャ
ノネル・トランジスタ・ソース・ドレイ７Ｐ型拡散層、
８・・・・・・Ｎテヤノネルトランジスタ・ソース・ド
レインＮ型Ｅ散／ｉｆ、 ９・・・・・・フィールド
・シリコ７酸化１［％ｌＯ・・・・・・ゲート・シリコ
ン酸化膜。FIG. 1(a) is a plan view showing a complementary MOS integrated circuit device according to an embodiment of the present invention, and FIG. 1(b) is a plan view showing a complementary MOS integrated circuit device according to an embodiment of the present invention.
FIG. 3 is a cross-sectional view taken along line A'. In the same figure, l...N-type silicon/substrate, 2.
...P type well, 3...N type diffusion layer, 4
...Contact for substrate electrode, 5...Tungsten/crystalline substrate electrode wiring, 6...
Polysilicon gate electrode wiring, 7...P channel transistor source/drain 7P type diffusion layer,
8...N Teyanonel transistor source/drain N type E dispersion/if, 9...Field silicon 7 oxide 1[%lO...Gate silicon oxide film.
Claims (1)
２導電型のウェルとからなる相補型ＭＯＳ集積回路装置
において、前記表面のＰＮ境界の近傍に前記ウェルまた
は基板電位をとるためのシリサイドまたはポリサイドか
らなる電極配線が形成されていることを特徴とする相補
型ＭＯＳ集積回路装置。In a complementary MOS integrated circuit device comprising a semiconductor substrate of a first conductivity type and a well of a second conductivity type formed on the surface thereof, silicide is used to take the well or substrate potential near a PN boundary on the surface. Alternatively, a complementary MOS integrated circuit device characterized in that an electrode wiring made of polycide is formed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59260362A JPS61137360A (en) | 1984-12-10 | 1984-12-10 | Complementary mos integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59260362A JPS61137360A (en) | 1984-12-10 | 1984-12-10 | Complementary mos integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61137360A true JPS61137360A (en) | 1986-06-25 |
Family
ID=17346880
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59260362A Pending JPS61137360A (en) | 1984-12-10 | 1984-12-10 | Complementary mos integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61137360A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01162350A (en) * | 1987-11-25 | 1989-06-26 | Marconi Electron Devices Ltd | Semiconductor structure |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5723260A (en) * | 1980-07-16 | 1982-02-06 | Toshiba Corp | Complementary mos semiconductor device |
| JPS5723259A (en) * | 1980-07-16 | 1982-02-06 | Toshiba Corp | Complementary type mos semiconductor device |
-
1984
- 1984-12-10 JP JP59260362A patent/JPS61137360A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5723260A (en) * | 1980-07-16 | 1982-02-06 | Toshiba Corp | Complementary mos semiconductor device |
| JPS5723259A (en) * | 1980-07-16 | 1982-02-06 | Toshiba Corp | Complementary type mos semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01162350A (en) * | 1987-11-25 | 1989-06-26 | Marconi Electron Devices Ltd | Semiconductor structure |
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