JPS607497Y2 - MOS transistor protection device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a protection device for MOS transistors.

In a conventional P-channel MO3IC or C3I,
When a positive signal such as noise enters from the input terminal, the P-type semiconductor region that forms the wiring part for the input signal as shown in Figure 1.
When the P-type semiconductor region B forming the wiring part of another circuit faces each other, a kind of PNP transistor is formed, which affects the other circuit including the P-type semiconductor region B.

In order to eliminate such adverse effects, the configuration shown in Figure 1 is actively introduced into the input circuit, and another P-type semiconductor region is formed opposite to the P-type semiconductor region that forms the input signal wiring section. A negative power supply potential is applied to this P-type semiconductor region to protect the input against positive signals.

FIG. 2 is a plan view pattern diagram of a semiconductor substrate designed for input protection, and FIG. 3 is a sectional view taken along line CC' in FIG.

Reference numeral 1 indicates a P-type semiconductor region forming a wiring section for input signals, and 2 indicates another P-type semiconductor region separately introduced into this input circuit, which is provided opposite to the P-type semiconductor region 1 and has a negative power supply potential - VDD is applied.

3 is an N-type semiconductor substrate connected to ground, and 4 is an insulating film covering the surface of the Devine.

With this configuration, a lateral PNP transistor as shown in the equivalent circuit of FIG. 3 is formed in the input circuit.

If a positive signal enters the input circuit, the PN junction formed by the P-type semiconductor region 1 and the N-type semiconductor region 3 will be forward biased, this PNP transistor will operate, and the transistor will enter the P-type semiconductor region 1. The positive signal is absorbed by the negative power supply of the P-type semiconductor region 3, thereby preventing an adverse effect on other circuits.

In order to make this protection operation more effective, it is possible to increase the length L of the opposing P-type semiconductor regions 1 and 2 and to narrow the interval W.

In particular, the interval W needs to be narrower than the interval between the P-type semiconductor region 1 containing the input signal and the P-type semiconductor region other than this input protection circuit.

However, if the spacing becomes too narrow, leakage between both P-type semiconductor regions 1 and 2 will increase, and the withstand voltage will decrease, which may pose a practical problem.

The present invention was devised in view of the above-mentioned problems in the input protection circuit, and will be explained below with reference to the drawings.

FIG. 5 is a cross section of an embodiment according to the present invention, in which a P
A type impurity region 2 is formed in an N-type semiconductor substrate 3, a gate electrode 5 is formed on an insulating film 4 covering the surface of the semiconductor substrate 3, and a protection device is formed in the NO3 structure.

In order to fulfill the protective function in the above NO3 structure,
While setting the P-type semiconductor region 2 to a negative power supply potential, the gate 5
is given a ground potential to which the semiconductor substrate 3 is connected.

This structure has the advantage that the interval W between the P-type semiconductor regions 1 and 2 can be narrower than that of a structure without a gate, and that the protection effect against positive force signals is also greater.

In the embodiment, the N-type semiconductor substrate 3 is set to the ground potential, but it may be set to other potentials.
If the potential of the semiconductor region 2 is more negative than that of the N-type semiconductor substrate 3, and if the gate 5 is also made of the same potential as the N-type semiconductor substrate 3 in FIG. It is possible to eliminate the influence of

As described above, according to the present invention, noise in a semiconductor device incorporating a transistor (MOS) can be easily reduced by providing an impurity region for an impurity region in addition to wiring provided on a semiconductor substrate to absorb noise. It can be removed quickly and reliably, and the reliability of the IC or LSI can be significantly improved.

Further, by forming the NO3 structure and applying the same potential to the gate as the substrate, leakage between impurity regions can be prevented and breakdown voltage can be increased, and an MO3 circuit with even better protection function can be obtained.

[Brief explanation of the drawing]

Fig. 1 is a sectional view showing a conventional example, Fig. 2 is a pattern diagram showing an improved example of the conventional example, Fig. 3 is a sectional view taken along line C-C' in Fig. 2, and Fig. 4 is an equivalent circuit diagram shown in Fig. 2. , FIG. 5 is a sectional view showing an embodiment of the present invention. 1.2...P-type semiconductor region, 3...N
shaped semiconductor substrate, 4... insulating film, 5...
Gate.

Claims (1)

[Scope of utility model registration request] In a semiconductor device incorporating a MOS transistor,
A semiconductor substrate exhibiting one conductivity type is provided with an impurity region exhibiting another conductivity type for forming a wiring portion, an impurity region exhibiting the other conductivity type is provided adjacent to the conductivity type, and the impurity region is While applying a reverse bias to the semiconductor substrate, a gate is provided on the substrate between the two impurity regions via an insulating film to form a MOS transistor structure, and a power supply potential having the same potential as that of the semiconductor substrate is applied to the gate. MO featuring
S) Protective devices for transistors.