CA1161968A - Protection circuit for integrated circuit devices - Google Patents
Protection circuit for integrated circuit devicesInfo
- Publication number
- CA1161968A CA1161968A CA000391274A CA391274A CA1161968A CA 1161968 A CA1161968 A CA 1161968A CA 000391274 A CA000391274 A CA 000391274A CA 391274 A CA391274 A CA 391274A CA 1161968 A CA1161968 A CA 1161968A
- Authority
- CA
- Canada
- Prior art keywords
- region
- layer
- protection circuit
- type
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000004224 protection Effects 0.000 title claims abstract description 28
- 239000000758 substrate Substances 0.000 claims description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 239000004065 semiconductor Substances 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 235000012239 silicon dioxide Nutrition 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- 230000005669 field effect Effects 0.000 claims description 2
- 239000000463 material Substances 0.000 claims description 2
- 239000002184 metal Substances 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 239000004020 conductor Substances 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 3
- 230000001052 transient effect Effects 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 230000006378 damage Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229910052582 BN Inorganic materials 0.000 description 1
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- BALXUFOVQVENIU-KXNXZCPBSA-N pseudoephedrine hydrochloride Chemical compound [H+].[Cl-].CN[C@@H](C)[C@@H](O)C1=CC=CC=C1 BALXUFOVQVENIU-KXNXZCPBSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/87—Thyristor diodes, e.g. Shockley diodes, break-over diodes
Landscapes
- Power Engineering (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Ceramic Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Bipolar Transistors (AREA)
- Bipolar Integrated Circuits (AREA)
- Thyristors (AREA)
Abstract
RCA 75,166 PROTECTION CIRCUIT FOR
INTEGRATED CIRCUIT DEVICES
Abstract of the Disclosure The protection circuit is a four layer PNPN device which includes a PMOS IGFET. The device is designed to pass current to ground when large transients are imposed across its two external terminals, thereby protecting the integrated circuit.
INTEGRATED CIRCUIT DEVICES
Abstract of the Disclosure The protection circuit is a four layer PNPN device which includes a PMOS IGFET. The device is designed to pass current to ground when large transients are imposed across its two external terminals, thereby protecting the integrated circuit.
Description
1 16~
75, l f PE~C)Tf,~ [ION_(,IRC ~ [ f (.)l~
NTF,CI A'~ F, ~_C I ~(,tJI'II DV~GI'S
Backyround of he Invention The present invention relates to a protectinn circuiL for integrated circuit devices.
In-tegrated circuits are often damaged hy vultaqe transients which overload one or more individual devices contain~d withirl th~
integrated circuit thereby melting or otherwise destroying the device. Heretofore, various devices and circuits have heen employcd for protective p-urposes on integra-ted circuit structures in ord~r to prevent their destruction by such transients. In the past, diodes and transistor circuits have been used for internal transient protect;ion.
While such devices provided some measure of protection to the integrated circui-ts in which they were included, additional protection has been desired .
Summary of the Invention The present invention relates to a protection circuit which provides transient protection for an integrated circuit. The protection circuit comprises a silicon controlled rec-tifier (SCR) which is constructed as a two terminal device, preferably as a part of the integrated circuit which is to be protected. The protection circuit comprises a PNPN structure in which an insulating layer overlies the N type region which is intermediate -to two P type regions. A
conductive layer overlies the insulating layer and makes con-tact to the N type region at the end of the PNPN s-tructure, thereby acting as the gate of the P channel MOS (PMOS) transistor while simultaneously acting as one of -the two terminals of the pro-tection circuit. Thus, if there is a transient which is negative with respect to the P t~lpe region at the end of the PNPN structure, the PM~S transistor will be turned on and the protection circuit will act like a diode through which the current can flow without harm to the protected circuit.
Brief Description of the Drawing FIG. 1 is a cross-sectional view of the preferred embodiment of -the present invention; and FIG. 2 is a schematic model of the invention.
Detai!ed Description of an Exempl~lr~_odime_t Referring to FIG. I, a cross-sectional view of the proteclion circuit 10, in accordance with the pre~erred embodiment of the 1 161~BB
present invention, is shown. Thc protection Cilcuit lU is comprise~
of a substrate 12, which is P ~ype silicon materiai in the r)referre(i embodiment o~ the invention. An N- epitaxial layer L~ forms a I~N
5 junction 16 with the P type substrate 12. A f' type region l8 is formed within the N type epitaxial layer l9, forming a PN junction 2f) with the layer 14. An N~ region 22 is formed within the E) Iype region 18, and it forms a PN junction 24 wil:h the P type region 18 A P-~ region 32 extends from the surface ot` the device 10 10 to make ohmic contact to substrate 12. The P+ region 32 preferably surrounds the device 10. A conductor 34 contacts the P+ region 32.
An insulating layer 26 overlies the surface of the device 10.
In the preferred embodiment of the invention, the insulating Layer 26 is comprised of silicon dioxide. A conduc-tive layer 28 over]ies the 15 insulating layer 26, overlying -the area where the N- type r egion 1~1 is adjacent the surface of the device 10, and at least partially overlying the P+ region 32 and the P type region 18. l:'he conductive layer also extends through an aperture 30 in the insulating layer 26 to make contact to the N+ region 22. The conductive layer 28 and 20 the conductor 34 are typically comprised of aluminum, bwt they may be comprised of any other suitable material, such as a trimetal system.
Referring now to FIG. 2, a schematic representation 100 of the protection circuit 10 of FIG. 1, is shown. In the schematic representation 100, the protection circuit comprises a PNP -transistor 25 Q1, an NPN transistor Q2, a P channel insulated gate field effect transistor (IGFET) Q3, and a pair ol capacitors C1, C2. 'rransistor Ql models -the P, N-, P regions 32, 14, 18 of FIG. 1. Accordin(lly, the emitter, base, and collector of transistor Q1 are referred -to using reference numerals 132, 114 and 118, respectively, in the 30 schematic represen-tation 100. Similarly, the transistor Q2 represents the N-, P, and N+ layers 14, 18, 22, respectively, of FIG. 1.
Accordingly, the collector, base, and emitter of transistor Q2 are represented by the reference numerals 114 (which is also the base of transistor Q1), 118 (which is also the collector of transistor Q1), and 122, respectively.
Similarly, the IGFET Q3 includes a drain 118, a source - 132, and a gate 128 which is also a terminal of the protection circuit 100. The capacitors C1 and C2 model the jwnction capacil:ance ol Lhe PN junctions 20 and 24 of the strwcture shown in F'lG. 1. 'l`he Iwo l 1~13~
7'" I fj~J
terminals 128, 13~ of the schematic represenlcllion 1()~ currespon(i to the two meta~ interconnects 28, 3~, respectively.
The protection circuit is similar in operation ~o a silicon 5 controlled rectifier (SCR) except that it is constructed as a Lwo terminal device which includes a P channel rGF E~'[' . Also, the protection circuit is designed to be triggere(l by either a high voltage across the two terminals 12~3, 134 or by a high rate of change of voltage (dv/dt) across the two terminals 128, 13~. Acccrdingly, 10 the protection circuit differs from a conventional SCE~ in that a conventional SCR is a three terminal device which is designed to avoid triggering based upon either the vo] tage between its anode and cathode or upon the rate of change of voltage hel:ween its anode and cathode.
In prac-tice, the cond-uctor 3a, (terminal 13~1) is connected to ground potential, whereas the conductor 28 (terminal 128) is connected across the circuitry which is designed to be protected.
Accordingly, if terminal 128 goes negative with respect to ground at a high rate, the protection circuit will be -turned on (terminals 128 20 and 134 will be electrically connected together) causing excess current to be passed to ground. Unlike the present protection device, a conventional SCR would have a low value resistor across capacitor C2 which would prevent such firing. In the event that there is a slow change of the voltage on terminal 128, a very small 25 current, on the order of nanoamps, will flow through transistor Q2 without causing the circuit to latch, because the total loop gain is selected to be less than ]. When the voltage on terminal 128 is negative enough, ~GFET Q3 will turn on causing transistor Q2 to turn on thereby providing sufficient loop gain to insure that -the 30 to-tal loop gain is greater than 1. Again, the pro-tection circuit will pass excess current to ground In order to manufacture the device of the present invention, one starts with a semiconductor substrate, preferably of P type (100) silicon having a resistivity of about 10 to 30 ohm-cm. An N type 35 epitaxial layer having a resistivity of about 1000 ohms/square is then grown to a thickness of between about 10 and 12 microns. Next, a layer of photoresist is applied over the surface of the device.
I'he photoresisl: is tlefined using a photomask and dev( lop~
to form openings through which a suit.lt)lt P type (lopanl, such as . 31~968 , ~
boron nitride, is deposiled and dirlused l;o form Ihe l'-~ isolaliorl regions 32. I'he P+ isolatk)n regions 32 have a surface concluctivify of about 5 ohms/square, and they contac~ the substrate l2 after 5 diffusion. Nex-t, a new photoresist layer is applied and defined usiny a second photomask to form an opening where the P ~ype re0ion l8 will be formed. A suitable acceptor impurity is deposited (either directly or by ion implantation), and it is diEfused to ~orm the P type reyion 18 to a depth of approximately 2.l to 2.2 micrometers. rlhc 10 P type region 18 will preferably have a surface resi~tiviî:y ol about 200 ohms/square.
In a similar manner the N+ region 22 is formed using 3 third photomask and photolithographic step. t)onor impurities are deposited and diffused to form the region 22 with a surface resistivity 15 of approximately 2-5 ohms/square.
Next, the oxide layer 26 is grown and openings are defined and formed therein using another photolithographic step.
Finally, a conductive layer 28 such as an aluminum layer, is applied to the surface of the device. The conductive layer 28 is 20 defined using a fourth photolithographic step, therehy completing the formation of the device 10.
75, l f PE~C)Tf,~ [ION_(,IRC ~ [ f (.)l~
NTF,CI A'~ F, ~_C I ~(,tJI'II DV~GI'S
Backyround of he Invention The present invention relates to a protectinn circuiL for integrated circuit devices.
In-tegrated circuits are often damaged hy vultaqe transients which overload one or more individual devices contain~d withirl th~
integrated circuit thereby melting or otherwise destroying the device. Heretofore, various devices and circuits have heen employcd for protective p-urposes on integra-ted circuit structures in ord~r to prevent their destruction by such transients. In the past, diodes and transistor circuits have been used for internal transient protect;ion.
While such devices provided some measure of protection to the integrated circui-ts in which they were included, additional protection has been desired .
Summary of the Invention The present invention relates to a protection circuit which provides transient protection for an integrated circuit. The protection circuit comprises a silicon controlled rec-tifier (SCR) which is constructed as a two terminal device, preferably as a part of the integrated circuit which is to be protected. The protection circuit comprises a PNPN structure in which an insulating layer overlies the N type region which is intermediate -to two P type regions. A
conductive layer overlies the insulating layer and makes con-tact to the N type region at the end of the PNPN s-tructure, thereby acting as the gate of the P channel MOS (PMOS) transistor while simultaneously acting as one of -the two terminals of the pro-tection circuit. Thus, if there is a transient which is negative with respect to the P t~lpe region at the end of the PNPN structure, the PM~S transistor will be turned on and the protection circuit will act like a diode through which the current can flow without harm to the protected circuit.
Brief Description of the Drawing FIG. 1 is a cross-sectional view of the preferred embodiment of -the present invention; and FIG. 2 is a schematic model of the invention.
Detai!ed Description of an Exempl~lr~_odime_t Referring to FIG. I, a cross-sectional view of the proteclion circuit 10, in accordance with the pre~erred embodiment of the 1 161~BB
present invention, is shown. Thc protection Cilcuit lU is comprise~
of a substrate 12, which is P ~ype silicon materiai in the r)referre(i embodiment o~ the invention. An N- epitaxial layer L~ forms a I~N
5 junction 16 with the P type substrate 12. A f' type region l8 is formed within the N type epitaxial layer l9, forming a PN junction 2f) with the layer 14. An N~ region 22 is formed within the E) Iype region 18, and it forms a PN junction 24 wil:h the P type region 18 A P-~ region 32 extends from the surface ot` the device 10 10 to make ohmic contact to substrate 12. The P+ region 32 preferably surrounds the device 10. A conductor 34 contacts the P+ region 32.
An insulating layer 26 overlies the surface of the device 10.
In the preferred embodiment of the invention, the insulating Layer 26 is comprised of silicon dioxide. A conduc-tive layer 28 over]ies the 15 insulating layer 26, overlying -the area where the N- type r egion 1~1 is adjacent the surface of the device 10, and at least partially overlying the P+ region 32 and the P type region 18. l:'he conductive layer also extends through an aperture 30 in the insulating layer 26 to make contact to the N+ region 22. The conductive layer 28 and 20 the conductor 34 are typically comprised of aluminum, bwt they may be comprised of any other suitable material, such as a trimetal system.
Referring now to FIG. 2, a schematic representation 100 of the protection circuit 10 of FIG. 1, is shown. In the schematic representation 100, the protection circuit comprises a PNP -transistor 25 Q1, an NPN transistor Q2, a P channel insulated gate field effect transistor (IGFET) Q3, and a pair ol capacitors C1, C2. 'rransistor Ql models -the P, N-, P regions 32, 14, 18 of FIG. 1. Accordin(lly, the emitter, base, and collector of transistor Q1 are referred -to using reference numerals 132, 114 and 118, respectively, in the 30 schematic represen-tation 100. Similarly, the transistor Q2 represents the N-, P, and N+ layers 14, 18, 22, respectively, of FIG. 1.
Accordingly, the collector, base, and emitter of transistor Q2 are represented by the reference numerals 114 (which is also the base of transistor Q1), 118 (which is also the collector of transistor Q1), and 122, respectively.
Similarly, the IGFET Q3 includes a drain 118, a source - 132, and a gate 128 which is also a terminal of the protection circuit 100. The capacitors C1 and C2 model the jwnction capacil:ance ol Lhe PN junctions 20 and 24 of the strwcture shown in F'lG. 1. 'l`he Iwo l 1~13~
7'" I fj~J
terminals 128, 13~ of the schematic represenlcllion 1()~ currespon(i to the two meta~ interconnects 28, 3~, respectively.
The protection circuit is similar in operation ~o a silicon 5 controlled rectifier (SCR) except that it is constructed as a Lwo terminal device which includes a P channel rGF E~'[' . Also, the protection circuit is designed to be triggere(l by either a high voltage across the two terminals 12~3, 134 or by a high rate of change of voltage (dv/dt) across the two terminals 128, 13~. Acccrdingly, 10 the protection circuit differs from a conventional SCE~ in that a conventional SCR is a three terminal device which is designed to avoid triggering based upon either the vo] tage between its anode and cathode or upon the rate of change of voltage hel:ween its anode and cathode.
In prac-tice, the cond-uctor 3a, (terminal 13~1) is connected to ground potential, whereas the conductor 28 (terminal 128) is connected across the circuitry which is designed to be protected.
Accordingly, if terminal 128 goes negative with respect to ground at a high rate, the protection circuit will be -turned on (terminals 128 20 and 134 will be electrically connected together) causing excess current to be passed to ground. Unlike the present protection device, a conventional SCR would have a low value resistor across capacitor C2 which would prevent such firing. In the event that there is a slow change of the voltage on terminal 128, a very small 25 current, on the order of nanoamps, will flow through transistor Q2 without causing the circuit to latch, because the total loop gain is selected to be less than ]. When the voltage on terminal 128 is negative enough, ~GFET Q3 will turn on causing transistor Q2 to turn on thereby providing sufficient loop gain to insure that -the 30 to-tal loop gain is greater than 1. Again, the pro-tection circuit will pass excess current to ground In order to manufacture the device of the present invention, one starts with a semiconductor substrate, preferably of P type (100) silicon having a resistivity of about 10 to 30 ohm-cm. An N type 35 epitaxial layer having a resistivity of about 1000 ohms/square is then grown to a thickness of between about 10 and 12 microns. Next, a layer of photoresist is applied over the surface of the device.
I'he photoresisl: is tlefined using a photomask and dev( lop~
to form openings through which a suit.lt)lt P type (lopanl, such as . 31~968 , ~
boron nitride, is deposiled and dirlused l;o form Ihe l'-~ isolaliorl regions 32. I'he P+ isolatk)n regions 32 have a surface concluctivify of about 5 ohms/square, and they contac~ the substrate l2 after 5 diffusion. Nex-t, a new photoresist layer is applied and defined usiny a second photomask to form an opening where the P ~ype re0ion l8 will be formed. A suitable acceptor impurity is deposited (either directly or by ion implantation), and it is diEfused to ~orm the P type reyion 18 to a depth of approximately 2.l to 2.2 micrometers. rlhc 10 P type region 18 will preferably have a surface resi~tiviî:y ol about 200 ohms/square.
In a similar manner the N+ region 22 is formed using 3 third photomask and photolithographic step. t)onor impurities are deposited and diffused to form the region 22 with a surface resistivity 15 of approximately 2-5 ohms/square.
Next, the oxide layer 26 is grown and openings are defined and formed therein using another photolithographic step.
Finally, a conductive layer 28 such as an aluminum layer, is applied to the surface of the device. The conductive layer 28 is 20 defined using a fourth photolithographic step, therehy completing the formation of the device 10.
Claims (7)
1. A protection circuit for integrated circuit devices comprising:
(a) a substrate of semiconductor material of a first conductivity type;
(b) a semiconductor layer of a second conductivity type on said substrate, said semiconductor layer having a surface;
(c) a first region which is of said first conductivity type and which extends into said semiconductor layer from said surface, whereby a PN junction is formed between said first region and the adjacent portions of said layer;
(d) a second region which is of said second conductivity type, said second region extending into said first region from said surface, whereby a PN junction is formed between said second region and said first region;
(e) a third region which is of said first conductivity type, said third region extending from said surface through said layer to said substrate, said third region being separated from said first region by a portion of said layer which portion extends to said surface;
(f) an insulating layer on said surface which extends over said surface between said second region and said third region and which overlies the portion of said first region which extends to said surface, said portion of said layer which extends to said surface, and at least portions of said second region and said third region on said surface;
(g) means for making electrical contact to said third region;
(h) conductive means overlying said insulating layer, said conductive means overlying at least portions of said first region and said third region, together with the portion of said layer lying therebetween, whereby said conductive means together with said insulating layer and said underlying regions and layer forms an insulated gate field effect transistor; and (i) means for simultaneously making electrical contact to said second region and to said conductive means.
-6- RCA 75,166
(a) a substrate of semiconductor material of a first conductivity type;
(b) a semiconductor layer of a second conductivity type on said substrate, said semiconductor layer having a surface;
(c) a first region which is of said first conductivity type and which extends into said semiconductor layer from said surface, whereby a PN junction is formed between said first region and the adjacent portions of said layer;
(d) a second region which is of said second conductivity type, said second region extending into said first region from said surface, whereby a PN junction is formed between said second region and said first region;
(e) a third region which is of said first conductivity type, said third region extending from said surface through said layer to said substrate, said third region being separated from said first region by a portion of said layer which portion extends to said surface;
(f) an insulating layer on said surface which extends over said surface between said second region and said third region and which overlies the portion of said first region which extends to said surface, said portion of said layer which extends to said surface, and at least portions of said second region and said third region on said surface;
(g) means for making electrical contact to said third region;
(h) conductive means overlying said insulating layer, said conductive means overlying at least portions of said first region and said third region, together with the portion of said layer lying therebetween, whereby said conductive means together with said insulating layer and said underlying regions and layer forms an insulated gate field effect transistor; and (i) means for simultaneously making electrical contact to said second region and to said conductive means.
-6- RCA 75,166
2. The protection circuit of Claim 1 wherein said substrate has P type conductivity.
3. The protection circuit of Claim 2 wherein said layer is an epitaxial layer of N type conductivity, said first region is of P
type conductivity and said second region is of N type conductivity.
type conductivity and said second region is of N type conductivity.
4. The protection circuit of Claim 3 wherein said substrate is comprised of silicon.
5. The protection circuit of Claim 4 wherein said insulating layer is comprised of silicon dioxide.
6. The protection circuit of Claim 5 wherein said conductive means is comprised of a layer of metal overlying said silicon dioxide layer.
7. The protection circuit of Claim 6 wherein said third region is a highly doped P type region which extends from the surface of said layer to the underlying P type substrate.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US21253480A | 1980-12-03 | 1980-12-03 | |
| US212,534 | 1980-12-03 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1161968A true CA1161968A (en) | 1984-02-07 |
Family
ID=22791421
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000391274A Expired CA1161968A (en) | 1980-12-03 | 1981-12-01 | Protection circuit for integrated circuit devices |
Country Status (7)
| Country | Link |
|---|---|
| JP (1) | JPS6048906B2 (en) |
| CA (1) | CA1161968A (en) |
| DE (1) | DE3147505A1 (en) |
| FR (1) | FR2495378A1 (en) |
| GB (1) | GB2088634B (en) |
| IT (1) | IT1139888B (en) |
| MY (1) | MY8500877A (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4484244A (en) * | 1982-09-22 | 1984-11-20 | Rca Corporation | Protection circuit for integrated circuit devices |
| IT1212767B (en) * | 1983-07-29 | 1989-11-30 | Ates Componenti Elettron | SEMICONDUCTOR OVERVOLTAGE SUPPRESSOR WITH PREDETINABLE IGNITION VOLTAGE WITH PRECISION. |
| JPS62295448A (en) * | 1986-04-11 | 1987-12-22 | テキサス インスツルメンツ インコ−ポレイテツド | Protective circuit against electrostatic discharge |
| US9281682B2 (en) * | 2013-03-12 | 2016-03-08 | Micron Technology, Inc. | Apparatuses and method for over-voltage event protection |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3940785A (en) * | 1974-05-06 | 1976-02-24 | Sprague Electric Company | Semiconductor I.C. with protection against reversed power supply |
| JPS55113358A (en) * | 1979-02-23 | 1980-09-01 | Hitachi Ltd | Semiconductor device |
-
1981
- 1981-11-26 GB GB8135659A patent/GB2088634B/en not_active Expired
- 1981-12-01 DE DE19813147505 patent/DE3147505A1/en active Granted
- 1981-12-01 IT IT25385/81A patent/IT1139888B/en active
- 1981-12-01 CA CA000391274A patent/CA1161968A/en not_active Expired
- 1981-12-02 JP JP56195101A patent/JPS6048906B2/en not_active Expired
- 1981-12-02 FR FR8122584A patent/FR2495378A1/en active Granted
-
1985
- 1985-12-30 MY MY877/85A patent/MY8500877A/en unknown
Also Published As
| Publication number | Publication date |
|---|---|
| GB2088634A (en) | 1982-06-09 |
| IT8125385A0 (en) | 1981-12-01 |
| JPS57120366A (en) | 1982-07-27 |
| JPS6048906B2 (en) | 1985-10-30 |
| DE3147505C2 (en) | 1991-02-28 |
| DE3147505A1 (en) | 1982-10-21 |
| IT1139888B (en) | 1986-09-24 |
| FR2495378B1 (en) | 1984-01-13 |
| GB2088634B (en) | 1984-08-15 |
| MY8500877A (en) | 1985-12-31 |
| FR2495378A1 (en) | 1982-06-04 |
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