JPS6211258A - Gaas semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To increase surge resistance by connecting a drain for a first FET to an input terminal for an active circuit at the next step and a source to a grounding terminal and each connecting a source and a gate for a second FET having the same threshold voltage to a gate and the source for the first FET by an offset gate and a drain to an input terminal. CONSTITUTION:When a polarity surge is applied to a second FET 11 from an input terminal 9, large reverse voltage is applied between a gate and a drain because the gate is grounded, previously the FET 11 is cut off, the surge is damped largely, and a FET 1 for driving is not annealed. When a negative polarity surge is applied to the terminal 9, the gate and the drain for the FET 11 are biassed in the forward direction. A space between the gate and the drain is increased and a voltage drop is generated owing to offset structure at that time, and the FET 11 is not burnt out. A signal passes through the FET 11 and is applied to a gate for the FET 1 when there is no surge. According to the constitution, the surge is damped or bypassed without damaging high-frequency characteristics, thus improving the surge-resistant performance of a GaAs IC device.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a GaAs semiconductor integrated circuit, and particularly to a GaAs semiconductor integrated circuit using a Schottky barrier type F E 'I' as a basic element.
Regarding semiconductor integrated circuits.

"Prior Art" GaAs semiconductor crystals have an electron mobility 5 to 6 times higher than Sj semiconductor crystals and have excellent high frequency characteristics, so active research and development is being carried out in various places.

Conventionally, this type of GaAs semiconductor integrated circuit uses an FET as shown in FIG. 2 as a basic element, and in order to reduce parasitic resistance and achieve ideal high frequency characteristics,
The distance between the ET gate electrode 21 and the ohmic electrodes (source electrode 22 and drain electrode 23) is usually 0.5 to 1.
The value of 971m is used.
Although the electrode spacing is reduced and high frequency characteristics are improved,
There is a problem that surge resistance performance deteriorates, and as a solution to this problem, a protective resistor is connected in series with the input terminal to improve surge resistance performance, but in this case, the protective resistor has a large resistance value. is required, which has the disadvantage of deteriorating high frequency characteristics.

An object of the present invention is to provide a Ga AS semiconductor integrated circuit that can improve anti-surge performance without impairing high frequency characteristics.

[Means for solving problems]

The Ga, As semiconductor integrated circuit of the present invention includes a first FET whose drain is connected to the input terminal of the next-stage active circuit and whose source is connected to the ground terminal, and the first FET with an off-cell toggle structure. a second FET having a threshold voltage at least equal to , a source connected to the gate of the first FET, a gate connected to the source of the first FET, and a drain connected to the input terminal. be done.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing one embodiment of the present invention.

In FIG. 1, an inverter section consisting of a drive FET (corresponding to the first FET) 1 and an active load FET 2 generates an inverted input signal, and the source follower FET 3,
Level shift diode 4, current source FET
The buffer section consisting of 5 serves to propagate the input inverted signal to the next stage logic circuit.

The gate of the drive FETI is connected to the source of the anti-surge FET 11 (corresponding to the second FET) at node 1 (), and the gate of the anti-surge FET 11 is connected to the source of the drive FETI at node 8. connected, node 8
is grounded.

Input terminal 9 to which the drain of anti-surge FET II is connected
Suppose that a large surge noise with positive polarity is applied to Since the gate of anti-surge FET 1 is grounded at node 8, a large reverse bias is applied between the gate and drain of anti-surge FET II.
II is in a state where it is turned off or close to it, the surge noise is greatly attenuated, and the gate part of the driving FETI is not burned out.

When negative polarity surge noise is applied to input terminal 9,
The gate and drain of the anti-surge FET II are biased in the forward direction, and a forward current flows through the gate 1- through the node 8, but the anti-surge FET II has an offset structure. Since the gate-drain distance is large, a voltage drop occurs, but the anti-surge FET II does not burn out.

In addition, in a situation where surge noise is not induced, a normal signal is applied from the input terminal 9 through the anti-surge FET II to the gate of the drive FET I, but the anti-surge FET
The on-resistance of II can be made sufficiently low by appropriately selecting the threshold voltage or gate width.

〔Effect of the invention〕

As explained above, the GaAs semiconductor integrated circuit of the present invention has a gate-grounded FET connected to the input terminal, and the FET
By connecting the drain of the input terminal to the input terminal, there is an effect that surge noise can be attenuated or bypassed without impairing high frequency characteristics, and surge resistance performance can be improved.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an embodiment of the present invention, and FIG. 2 is a sectional view of a Schottky barrier type FET in a general GaAs semiconductor integrated circuit. 1... Drive FET, 2... Active load FET, 3...
... Source follower FET, 4... Level shift diode, 5... Current source FBT, 6... Negative bias power supply, 7... Positive bias power supply, 8... Grounding point, 9... Input terminal, 11... anti-surge FET,
21...gate, 22...source, 23...drain.

Claims (1)

[Claims] a first FET having a drain connected to an input terminal of a next-stage active circuit and a source connected to a ground terminal; a second FET connected to the gate of the FET, a second FET having a gate connected to the source of the first FET and a drain connected to the input terminal.
aAs semiconductor integrated circuit.