JPS61186018A - Field effect transistor logic circuit - Google Patents

Abstract

PURPOSE:To drive a buffer by one stage of an SCFL logic circuit by obtaining two inputs, 'true' and 'false' required for a totem pole type buffer from an output of the SCFL logic circuit. CONSTITUTION:An input signal voltage is impressed to a gate electrode 60 of an FET3 and a comparison voltage is impressed to a gate electrode 61 of an FET4. The difference between the input signal and the comparison voltage is amplified and appears output terminals 20, 21 of the SCFL. In general, the FETs 3, 4 are biased so as to be operated within a drain current saturation region. The outputs 20, 21 of the SCFL connect to the gate electrodes of FETs 6, 7 of the buffer circuit, one FET is turned on and the rest is turned off. Thus, an output is obtained from an output terminal 30.

Description

Detailed Description of the Invention (Industrial Application Field) The present invention relates to a logic circuit using stable field effect transistors, and particularly to a source-coupled logic circuit (hereinafter referred to as 5CFL).
This field-effect transistor logic circuit consists of a totem-pole type buffer and a totem-pole buffer.

(Prior art and its problems) In GaAs semiconductors, electrons move to the Si# ratio fljJ5
Since it is large, and when further integration is desired, semi-P3 edge GaAs can be used as a substrate, making it possible to reduce the parasitic capacitance of the circuit. Therefore, a logic circuit using a GaAs Schottky gate field effect transistor (hereinafter referred to as GaAs MFj8FF+T) having a GaAs semiconductor as an operating layer is capable of higher-speed logic operation than a logic circuit using an 8i bipolar transistor. However, Ga
Logic circuits using As M138FETs have low load driving capability, so when trying to drive a large load, conventionally, as shown in Figures 4 and 5, the load on the circuit was reduced by adding a buffer circuit to the inverter. Circuit systems were used to increase drive capability and enable high-speed logic operations.

In FIG. 4, resistors 1 and 2 are connected to a terminal 100 of a power supply and are of the enhancement type GaAsMF! 8F
Connected to the drain electrodes of FjTs 3 and 4. The resistor 5 is connected to the source electrode of the 8CPL MBSFET, 3.4, and the power supply terminal 101. In the buffer circuit, the drain electrode of the enhancement type PET 16 is connected to the power supply terminal 100, and the gate electrode is connected to the output 20 of the 8CFL.
The source electrode is connected to the node 41.

A diode 17 is installed between the node 41 and the output terminal 30. The resistor 18 is a load of the buffer circuit and is connected to the power supply connection terminal 102. In such a circuit,
Current always flows through the buffer circuit, and although it is possible to drive a large load by increasing the gate width of the PET in the buffer circuit, this has the drawback of increasing the power consumption of the circuit. On the other hand, since Ga silicon has a higher thermal resistance than Si, the large power consumption of the circuit is disadvantageous because it may deteriorate the characteristics of the element.

In FIG. 5, a normal enhancement type FF! T
7.15.23 and depletion type FET6.14.1
This is a logic circuit that drives a totem pole type buffer with the output of a two-stage inverter made up of 9. The depletion type F13T6 buffer circuit has a drain electrode connected to the power supply terminal 100, a gate electrode connected to the output of the second stage inverter, and a source electrode connected to the output terminal 30. Further, the drain electrode of the enhancement PET 7 is connected to the output terminal 30, the gate electrode is connected to the output of the first stage inverter, and the source electrode is connected to the terminal 102 of the power supply. This circuit turns either FHT ON or OFF depending on the inverter output.
By doing so, the output can be obtained. Note that 60 is an input terminal. In such a circuit, even if the gate width of the buffer is increased to drive a large load, the power consumption of the circuit does not increase because current flows through the buffer only during the charging and discharging time of the load capacitance. However, the input of the buffer requires two inputs, ``true'' and ``false'', and the output of the logic circuit is determined by the delay time of the output of the second-stage inverter, and the operating speed is delayed by one inverter stage. Therefore,
With this method, high-speed logic operations cannot be expected.

(Objective of the Present Invention) An object of the present invention is to obtain a logic circuit that is capable of high-speed logic operation even when driving a large load and has low power consumption.

(Structure of the Invention) A logic circuit of the present invention includes a first load element having one end connected to a first power supply connection terminal and the other end connected to a first node, and one end connected to the first power supply connection terminal. terminal and the other end is the second
a second load element connected to a node, a drain electrode connected to the first node, a gate electrode connected to the first input terminal, and a first load element connected to the third node;
a second PF8T having a drain electrode connected to the second node, a gate electrode connected to the second input terminal, and a source electrode connected to the third node; A source-coupled logic circuit having a third load element whose other end is connected to the second power supply connection terminal and whose drain electrode is connected to the first power supply connection terminal and whose gate 1! a first depletion type F in which a frame is connected to the first node and a source electrode is connected to the output terminal;
]13T, the drain electrode is connected to the output terminal, the gate electrode is connected to the second node, and the source electrode is connected to the third node.
Features (Functions) In the logic circuit according to the present invention, the logic circuit includes a totem-pole type buffer having a third FET connected to the power supply connection terminal of the totem-pole type buffer. 8 “false” two inputs
By obtaining the output from the 0FL logic circuit, it is possible to drive the buffer with one stage of 8CFLs. Therefore, higher-speed logic operation is possible than in a logic circuit as shown in FIG. 5, which is configured with a normal two-stage inverter. Furthermore, even if the buffer gate width is increased to drive a large load,
In the buffer circuit, current flows only while charging and discharging the load connected to the output terminal, so power consumption in a steady state is low.

(Example) FIG. 1 shows a first embodiment of a logic circuit according to the present invention.

Note that the same components as those in FIG. 1 will be described with the same numbers. The present invention uses an 8CFL logic circuit to drive a totem pole type buffer. Resistors 1 and 2 are
They are each connected to a power supply terminal 100 and to the drain electrodes of enhancement type GaAsME8F]13T3 and 4, respectively. Resistor 5 is 80F'L Ml! i
It is connected to the source electrode of 8F'BT and the power supply terminal 101.

On the other hand, the buffer circuit is a deplacement type GaAsMB.
The drain electrode of SFgT6 is connected to the terminal 100 of the power supply, the gate electrode is connected to the output terminal 20 of 8CFL,
A source electrode is connected to the output terminal 30, a drain electrode of the enhancement type GaAsME8FBT7 is connected to the output terminal, a gate electrode is connected to the output terminal 21 of the 8CFL, and a source electrode is connected to the terminal 102 of the power supply. An input signal n voltage is applied to the gate electrode 60 of FBT3, and a comparison voltage is applied to the gate electrode 61 of FBT4. The difference between the input signal and the comparison voltage is amplified to 5CFL
appears at output terminal 20.21 of. Generally FBT3 and F
B'r4 is biased to operate within the drain current saturation region. The outputs 20.21 of 5CFL are connected to the gate electrodes of FETs 6.7 of the buffer circuit, and one of the FBTs is turned on and the rest are turned on.
Set it to “F” state. Therefore, an output can be obtained from the output terminal 30. In addition, PE'r6 of the buffer circuit is
It is necessary to use the deplacement type M B S F B T so that the output 20 of the 5CFL is in the "ON" state when it is at a high level. FIG. 2 shows a second embodiment according to the present invention, in which a depletion type G is used instead of the resistors 1 and 2.5.
This uses an MFj8FET.

FIG. 3 shows a third embodiment of the present invention, in which all PBTs are of the depletion type. In this case 5CF
When the L output 21 is at low level, the FET 13 is “OFF”.
It is necessary to design the system so that the

(Effects of the Invention) In the logic circuit according to the present invention, by obtaining the two inputs "true" and "false" of the totem pole type buffer from the output of 80FL, the buffer can be driven with one stage of 8CFL.
High-speed logic operation is possible compared to conventional logic circuits configured with two-stage inverters. Furthermore, when driving a large load, power consumption can be reduced even if the gate width of the PET of the buffer circuit is increased. Therefore, even in a semiconductor having a high thermal resistance such as GaAa, high-speed logic operation is possible without deteriorating the performance of the device.

[Brief explanation of the drawing]

1 to 3 are diagrams showing embodiments of the present invention. FIG. 4.5 is a diagram showing a conventional example. 1.2,5,18...Resistance, 3,4,7,15°16
．． 23...Enhancement type Mg8F'ET. 6.8, 9, 10, 11, 12, 13, 14.19...
・Deplacement type MESFgT, 17...Diode, 60.61...Input terminal, 30...Output terminal,
100.101.102...Power connection terminal, 20゜2
1.22, 41, 50, 51... Nodes. l00-tei 2 diagram

Claims (1)

[Claims] a first load element having one end connected to the first power supply connection terminal and the other end connected to the first node; and a first load element having one end connected to the first power supply connection terminal and the other end connected to the second node. and a first MESFET having a drain electrode connected to the first node, a gate electrode connected to the first input terminal, and a source electrode connected to the third node. , a drain electrode is connected to the second node, a gate electrode is connected to the second input terminal, and a source electrode is connected to the third node.
a source-coupled logic circuit having a second MESFET connected to the node, and a third load element having one end connected to the third node and the other end connected to the second power supply connection terminal; a first depletion type FET having a drain electrode connected to the first power supply connection terminal, a gate electrode connected to the first node, and a source electrode connected to the output terminal;
and a totem-pole buffer having a third MESFET whose drain electrode is connected to the output terminal, whose gate electrode is connected to the second node, and whose source electrode is connected to the third power supply connection terminal. Features a field-effect transistor logic circuit.