JP2010010305A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device where influence (potential interference) on circumferential device formation regions is suppressed even when reference potential is rapidly changed in a high-potential reference circuit, and a malfunction hardly occurs; and also to provide an inexpensive method for manufacturing the semiconductor device. <P>SOLUTION: A semiconductor substrate 11 is constituted of a first semiconductor layer 1 on the main surface and a second semiconductor layer 2 on the back surface with an embedding insulating film 3 between the layers. The first semiconductor layer 1 includes a low-potential reference circuit and a high-potential reference circuit. The respective device formation regions D are mutually separated by insulation by an insulating separation trench 4 in the semiconductor device 20. A porous silicon region P1 is formed on the second semiconductor layer 2 so as to reach the embedding insulating film 3. The second semiconductor layer 2 is separated into a plurality of field regions F1, F2 by partitioning with the porous silicon region P1. The field regions F1, F2 are fixed in potential in the semiconductor device 20. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention provides a low potential reference circuit portion and a high potential on a first semiconductor layer on the main surface side of an SOI (Silicon On Insulator) structure semiconductor substrate having a buried insulating film (silicon oxide film, silicon nitride film, laminated film thereof, etc.). The present invention relates to a semiconductor device provided with a potential reference circuit portion and a manufacturing method thereof.

  A semiconductor device in which a low potential reference circuit portion and a high potential reference circuit portion are provided in a first semiconductor layer on the main surface side of an SOI structure semiconductor substrate having a buried insulating film is disclosed in, for example, Japanese Patent Laying-Open No. 2006-93229 (patent) Document 1) and Japanese Patent Application Laid-Open No. 2007-266561 (Patent Document 2).

  8 and 9 are representative examples of conventional high-voltage ICs for driving an inverter disclosed in Patent Documents 1 and 2, FIG. 8 is a schematic top view of the high-voltage IC 90, and FIG. FIG.

The high voltage IC 90 shown in FIGS. 8 and 9 is formed on the SOI substrate 10 having the buried insulating film 3. The SOI layer 1 of the SOI substrate 10 has a low potential (GND) reference circuit portion and a high potential (floating). ) A reference circuit section is provided. As shown in FIG. 9, each device formation region in the low potential reference circuit portion and the high potential reference circuit portion includes a buried insulating film 3 and an insulating isolation trench 4 (side wall oxide film 4s) reaching the buried insulating film 3. Are isolated (dielectric) from each other. The SOI substrate 10 is formed by bonding substrates, and below the buried insulating film 3 is a thick support substrate 2 made of silicon (Si). In FIG. 8, the illustration of the insulating isolation trench 4 is omitted for simplification.
JP 2006-93229 A JP 2007-266561 A

  In the high voltage IC 90 shown in FIGS. 8 and 9, the device forming regions of the low potential reference circuit portion and the high potential reference circuit portion are surrounded by the buried insulating film 3 and the insulating isolation trench 4 as described above. For this reason, unlike a high-voltage IC in which, for example, a bulk single crystal silicon substrate is used and device formation regions of the above circuits are separated by pn junctions, parasitic transistor operation does not occur. However, the high voltage IC 90 has a structure in which a kind of capacitors C1 to C3 are formed with the embedded insulating film 3 interposed therebetween, as illustrated in FIG. Therefore, when a suddenly changing voltage is applied to an arbitrary device formation region separated by the insulating isolation trench 4, the displacement current is changed to another device formation region via the support substrate 2 due to capacitive coupling by the capacitors C1 to C3. Will flow.

  Thus, in an integrated device using SOI or DIW (Dielectric Isolated Wafer), each isolated device forming region is reliably insulated from other device forming regions in terms of direct current (DC). However, in an alternating current (AC) or transient manner, a dielectric film (insulator film) for insulation isolation serves as a coupling capacitance, causing a displacement current to flow, causing potential interference between devices. In the case of the SOI structure semiconductor substrate 10 shown in FIG. 9, this potential interference propagates mainly through the buried insulating film 3 having a large coupling area.

  More specifically, in the high potential (floating) reference circuit portion of the high voltage IC 90, the reference potential varies in the range of 0 to several hundred volts. As shown in FIG. 9, when the support substrate 2 is fixed to GND, a potential difference of several hundred volts is repeatedly generated between the SOI layer 1 and the support substrate 2 in the high potential reference circuit unit. For this reason, an undesired displacement current flows through each device in the high potential reference circuit section, and malfunction is likely to occur. Further, when the support substrate 2 is in a floating state (floating) or the potential of the support substrate 2 is not sufficiently fixed, the potential of the support substrate 2 is changed due to a change in the reference potential on the high potential reference circuit side. It fluctuates and adversely affects both the low potential reference circuit part and the high potential reference circuit part in the SOI layer 1.

  In particular, in-vehicle inverter driving high voltage ICs handle voltages of several hundred V to several hundreds of V, and the voltage changes in a short time of the order of μs, so that a very large displacement current flows. As a specific example, when the reference potential 1000 V changes in 1 μs in the circuit part of the half of the chip, the displacement current flowing in the 30 μm square device formation region at a distance of 1 mm is calculated to be about 0.1 μA. Actually, the fluctuation rate dV / dt of the reference potential is required to be 20 kV / μs or more, and in this case, a current of the order of μA or more flows. Therefore, for example, when such a displacement current is superimposed on the base current of the bipolar transistor element, a highly accurate transistor operation cannot be expected.

  Accordingly, the present invention is a small semiconductor device in which a low potential reference circuit portion and a high potential reference circuit portion are provided in a first semiconductor layer on the main surface side of an SOI structure semiconductor substrate having a buried insulating film, Even when there is a steep change in the reference potential in the reference circuit portion, the influence on the surrounding device formation region (potential interference) can be suppressed, and a semiconductor device in which malfunction is unlikely to occur, and the cost of the semiconductor device are low It aims to provide a simple manufacturing method.

  The semiconductor device according to claim 1 is a semiconductor having an SOI structure including a first semiconductor layer made of silicon on the main surface side and a second semiconductor layer made of silicon on the back surface side with a buried insulating film interposed therebetween. In the substrate, a low potential reference circuit portion and a high potential reference circuit portion are provided in the first semiconductor layer on the main surface side, and each device formation region in the low potential reference circuit portion and the high potential reference circuit portion includes A semiconductor device that is insulated and isolated from each other by an isolation trench that reaches a buried insulating film, wherein the second semiconductor layer on the back surface side is more porous than the second semiconductor layer so as to reach the buried insulating film. A porous silicon region is formed, partitioned by the porous silicon region, the second semiconductor layer is separated into a plurality of field regions, and the field region is fixed in potential. It is characterized in Rukoto.

  The semiconductor device is a small semiconductor device in which a low potential reference circuit portion and a high potential reference circuit portion are provided in a first semiconductor layer on the main surface side of an SOI structure semiconductor substrate having a buried insulating film. The device formation regions in the low-potential reference circuit section and the high-potential reference circuit on the main surface side are insulated and isolated from each other by an insulating isolation trench that reaches the buried insulating film. Further, the second semiconductor layer on the back surface side is divided by a porous silicon region reaching the buried insulating film and separated into a plurality of field regions. In the semiconductor device, the field region is The potential is fixed.

  Therefore, in the above semiconductor device, each field region on the back side is appropriately fixed at a preferable reference potential, so that, for example, even when there is a steep change in the reference potential in the high potential reference circuit section, the surrounding devices The influence (potential interference) on the formation region can be suppressed. Thus, the semiconductor device can be a semiconductor device that is unlikely to malfunction.

  For example, as in claim 2, the field region immediately below the high potential reference circuit unit is fixed at the same reference potential as the high potential reference circuit unit, and the field region immediately below the low potential reference circuit unit is The field region is fixed at the same ground (GND) reference potential as that of the low potential reference circuit section.

  As a result, the first semiconductor layer on the main surface side and the second semiconductor layer on the back surface side sandwiching the buried insulating film have the same reference potential in the high potential reference circuit portion and the low potential reference circuit portion, respectively. Displacement current due to capacitive coupling via is suppressed. Therefore, for example, compared with the case where the porous semiconductor region is not formed in the second semiconductor layer and the whole of the second semiconductor layer is fixed to the ground (GND) reference potential, any of the high potential reference circuit portions Even if there is a steep change in the reference potential in the device formation region, the influence on the surrounding device formation region can be suppressed.

  Further, since the porous silicon region has a higher resistance than the surrounding field region, it is possible to suppress leakage current.

  The semiconductor device according to claim 3, wherein the insulating isolation trench is an insulating isolation trench made of a sidewall oxide film and embedded polycrystalline silicon, and the embedded polycrystalline silicon penetrates the embedded insulating film. The field region is connected to the field region, and the field region can be configured to have a potential fixed from the main surface side of the semiconductor substrate via the buried polycrystalline silicon.

  According to this, since the potential of each field region on the back surface side can be fixed from the main surface side, the wiring can be easily handled, and the manufacturing cost can be reduced to provide an inexpensive semiconductor device.

  The semiconductor device may have a structure in which the porous silicon region is extended over the entire surface of the rear surface portion of the second semiconductor layer. Thereby, the entire back surface side of the semiconductor substrate can be protected by the porous silicon region extending in the surface layer portion. For this reason, for example, even when each field region is fixed to a different reference potential, it can be easily mounted on a lead frame or the like.

  According to a fifth aspect of the present invention, the semiconductor device may have a structure in which the porous silicon region is oxidized. In this case, the porous silicon region can be an insulating region instead of a high resistance region. In this case as well, it goes without saying that the potential interference to the surrounding device formation region can be suppressed by fixing the potential of each field region.

  As described above, the semiconductor device is a small semiconductor device in which the low potential reference circuit portion and the high potential reference circuit portion are provided in the first semiconductor layer on the main surface side of the SOI structure semiconductor substrate having the buried insulating film. Even when there is a steep fluctuation of the reference potential in the high potential reference circuit portion, the influence on the surrounding device formation region (potential interference) can be suppressed, and the semiconductor device is less likely to malfunction. can do.

  Therefore, the semiconductor device requires a low potential reference circuit portion and a high potential reference circuit portion, and these circuit portions are formed on a single semiconductor substrate for miniaturization. Suitable for high voltage IC. Further, as described in claim 7, it is particularly suitable as a vehicle-mounted semiconductor device that requires handling of a high voltage of several hundred volts to several hundreds of volts.

  The invention described in claims 8 to 11 relates to a method of manufacturing the semiconductor device.

  According to an eighth aspect of the present invention, an SOI structure semiconductor substrate comprising a first semiconductor layer made of silicon on the main surface side and a second semiconductor layer made of silicon on the back surface side with a buried insulating film interposed therebetween. In the first semiconductor layer on the main surface side, a low potential reference circuit portion and a high potential reference circuit portion are provided, and each device formation region in the low potential reference circuit portion and the high potential reference circuit portion is embedded in the first semiconductor layer. Insulating and isolating from each other by an isolation trench that reaches the insulating film, and a porous silicon region that is more porous than the second semiconductor layer is formed in the second semiconductor layer on the back surface side so as to reach the buried insulating film. And a method of manufacturing a semiconductor device, wherein the second semiconductor layer is separated into a plurality of field regions, and the field regions are fixed in potential by being partitioned by the porous silicon region There are, the porous silicon region, it is characterized by formed by anodization.

  According to this, the porous silicon region can be easily formed only by adding an anodizing treatment step, and the semiconductor device according to claim 1 can be manufactured at low cost, which is unlikely to cause malfunction. .

  In the case of manufacturing a semiconductor device in which the isolation isolation trench according to claim 3 is made of a sidewall oxide film and buried polycrystalline silicon, the buried polycrystalline silicon has the buried insulating film formed as described in claim 9. The insulating isolation trench is formed in advance so as to pass through and connected to the second semiconductor layer, and using the predetermined buried polycrystalline silicon connected to the second semiconductor layer as a positive electrode, The porous silicon region is preferably formed by anodization.

  According to this, since the formation of the back electrode on the semiconductor substrate can be omitted as the positive electrode for the anodizing treatment, the manufacturing cost can be further suppressed.

  In the manufacturing method, as described in claim 10, the anodization is performed in a two-step process, and the porous silicon region extends over the entire surface of the back surface layer portion of the second semiconductor layer. Can be extended. Thus, the semiconductor device described in claim 4 can be manufactured.

  Further, as described in claim 11, the formed porous silicon region may be oxidized. Thus, the semiconductor device described in claim 5 can be manufactured.

  The best mode for carrying out the present invention will be described below with reference to the drawings.

  FIG. 1 is a schematic sectional view of a semiconductor device 20 as an example of the semiconductor device of the present invention. In the semiconductor devices of the examples shown below, the same reference numerals are given to the same parts as those of the semiconductor device (high voltage IC) 90 shown in FIGS. Further, the top view of the semiconductor device 20 in FIG. 1 is the same as that of the semiconductor device 90 shown in FIG.

  A semiconductor device 20 shown in FIG. 1 includes a first semiconductor layer 1 made of silicon on the main surface side and a second semiconductor layer (support substrate) 2 made of silicon on the back surface side with a buried insulating film 3 interposed therebetween. The semiconductor substrate 11 having an SOI structure is formed. The semiconductor device 20 is an in-vehicle inverter driving high voltage IC similar to the semiconductor device 90 shown in FIG. 9, and a low potential (GND) reference circuit section is formed on the first semiconductor layer 1 on the main surface side of the semiconductor substrate 11. And a high potential (floating) reference circuit section. The device formation regions D in the low potential reference circuit portion and the high potential reference circuit portion of the first semiconductor layer 1 are insulated and isolated from each other by the insulating isolation trench 4 reaching the buried insulating film 3.

  On the other hand, unlike the semiconductor device 90 shown in FIG. 9, the semiconductor device 20 of FIG. 1 is more porous than the second semiconductor layer 2 so as to reach the buried insulating film 3 in the second semiconductor layer 2 on the back surface side. A porous silicon region P1 is formed. The second semiconductor layer 2 is separated into two field regions F1 and F2 by being partitioned by the porous silicon region P1. Further, in the semiconductor device 20 of FIG. 1, the insulating isolation trench 4 is made of a sidewall oxide film 4s and a high impurity concentration buried polycrystalline silicon 4p, and the buried polycrystalline silicon 4p penetrates the buried insulating film 3, It is connected to each field area F1, F2. The field region F2 immediately below the high potential (floating) reference circuit portion is fixed at the same high voltage reference potential Vxx as the high potential reference circuit portion, and the field region F1 directly below the low potential reference circuit portion is The potential is fixed to the same ground (GND) reference potential 0V as the low potential reference circuit section. Each of the field regions F1 and F2 is fixed in potential from the main surface side of the semiconductor substrate 11 through the buried polycrystalline silicon 4p.

  2A and 2B are schematic bottom views of the semiconductor devices 21 and 22, respectively, which are the same semiconductor devices as the semiconductor device 20 shown in FIG.

  In the semiconductor device 21 of FIG. 2A, a porous silicon region P2 is formed across the chip, and the second semiconductor layer 2 is separated into two field regions F3 and F4. In the semiconductor device 22 of FIG. 2B, the porous silicon region P3 is formed so as to surround the high potential reference circuit portion directly above, and the second semiconductor layer 2 is formed in the two field regions F5 and F6. It is separated.

  As described above, in each of the semiconductor devices 20 to 22 illustrated in FIGS. 1 and 2, the low potential reference circuit is formed on the first semiconductor layer 1 on the main surface side of the SOI structure semiconductor substrate 11 having the buried insulating film 3. And a high-potential reference circuit portion. The device formation regions D in the low-potential reference circuit section on the main surface side and the high-potential reference circuit are insulated and isolated from each other by the insulating isolation trench 4 reaching the buried insulating film 3. Further, the second semiconductor layer 2 on the back surface side is partitioned by porous silicon regions P1 to P3 reaching the buried insulating film 3, and is separated into two field regions F1, F3, F5 and field regions F2, F4, F6. It has a structure.

  The field regions F2, F4, F6 immediately below the high potential reference circuit portion are fixed to the same reference potential Vxx as the high potential reference circuit portion, and the field regions F1, F3, F3 immediately below the low potential reference circuit portion are fixed. F5 is fixed at the same ground (GND) reference potential as the low potential reference circuit section. As a result, the first semiconductor layer 1 on the main surface side and the second semiconductor layer 2 on the back surface side sandwiching the buried insulating film 3 have the same reference potential in the high potential reference circuit portion and the low potential reference circuit portion, respectively. Displacement current due to capacitive coupling through the buried insulating film 3 is suppressed. Therefore, unlike the semiconductor device 90 shown in FIG. 9, for example, the porous silicon regions P1 to P3 are not formed in the second semiconductor layer 2, and the entire second semiconductor layer 2 is set to the ground (GND) reference potential. Compared to the case of fixing, even if there is a steep change in the reference potential in any of the device formation regions D in the high potential reference circuit portion, the influence on the surrounding device formation regions D can be suppressed.

  In addition, since the porous silicon regions P1 to P3 of the semiconductor devices 20 to 22 illustrated in FIGS. 1 and 2 have higher resistance than the surrounding field regions F1 to F6, it is possible to suppress leakage current. For example, in order to set the leakage current between field regions having a potential difference of 1000 V to 100 μA or less, the resistance value of the porous silicon region may be 10 kΩ or more. Here, considering the case where the chip size is 4 mm square, the thickness of the second semiconductor layer (support substrate) 2 is 400 μm, and the width is 400 μm, the porous silicon region is separated into two field regions, the required specific resistance ρ is It may be 4 kΩ · cm or more. This is a value that can be easily achieved by forming a porous silicon region by anodizing treatment described later.

  The porous silicon regions P1 to P3 of the semiconductor devices 20 to 22 may have a structure formed by oxidation treatment. In this case, the porous silicon regions P1 to P3 can be formed as insulating regions instead of high resistance regions. Also in this case, it goes without saying that the potential interference to the surrounding device formation region D can be suppressed by fixing the potentials of the field regions F1 to F6.

  Further, in the semiconductor devices 20 to 22 illustrated in FIGS. 1 and 2, the second semiconductor layer 2 on the back surface side in the porous silicon regions P <b> 1 to P <b> 3 is replaced with the high potential reference circuit portion and the low potential reference circuit on the main surface side. It was separated into two field regions F1, F3, F5 and field regions F2, F4, F6 corresponding to the part. However, the present invention is not limited to this, and the second semiconductor layer 2 may be separated into an arbitrary plurality of field regions in the porous silicon region reaching the buried insulating film 3. Also in this case, the influence (potential interference) on the surrounding device formation regions can be suppressed by appropriately fixing the potential of each field region to a preferable reference potential corresponding to the device formation region immediately above it. Accordingly, the semiconductor device can be a semiconductor device that is unlikely to malfunction.

  The semiconductor device 20 of FIG. 1 has a structure in which each field region F1, F2 is fixed in potential from the main surface side of the semiconductor substrate 11 through the buried polycrystalline silicon 4p. As described above, the insulating isolation trench 4 is constituted by the side wall oxide film 4s and the buried polycrystalline silicon 4p, and the buried polycrystalline silicon 4p is connected to each field region through the buried insulating film 3, whereby the main surface is obtained. In addition to the device formation region on the side, each field region on the back side can be fixed at the potential from the main surface side. As a result, the wiring can be easily handled, the manufacturing cost can be reduced, and an inexpensive semiconductor device can be obtained. However, the present invention is not limited to this, and as will be described later, a dedicated electrode may be formed on the back side of the semiconductor substrate 11 to fix the potential of the field regions F1 and F2.

  Next, a description will be given of a method using anodization in forming the porous silicon region P1 as a preferred method for manufacturing the semiconductor device 20 shown in FIG.

  FIG. 3 is a schematic cross-sectional view of the semiconductor device 20 in the middle of manufacture using anodization.

  In manufacturing the semiconductor device 20 of FIG. 1, each structure of a desired device is first formed in the first semiconductor layer 1 on the main surface side of the semiconductor substrate 11 using a normal semiconductor manufacturing process.

  In the course of this manufacturing process, the sidewall oxide film 4s and the buried polycrystalline silicon 4p having a high impurity concentration are formed, and the buried polycrystalline silicon 4p penetrates the buried insulating film 3 and is connected to the second semiconductor layer 2. The insulating isolation trench 4 is formed in advance. Specifically, a trench penetrating through the buried insulating film 3 is formed first, and a sidewall oxide film 4s is formed (the oxide film is formed in the trench and the oxide film at the bottom of the trench is removed), and then a large number of trenches are formed in the trench. Crystal silicon 4p is embedded, and further, a p-type impurity is added to the polycrystalline silicon 4p by, for example, ion implantation. The implanted p-type impurity diffuses into the second semiconductor layer 2 deeper than the interface with the buried insulating film 3 by a heat treatment in a subsequent device formation process, and the buried polycrystalline silicon 4p is used as a p-type polycrystalline electrode. It will be ready. The buried polycrystalline silicon 4p is connected to a predetermined portion by the same metal wiring for connection as other devices.

  Next, as shown in FIG. 3, the buried polycrystalline silicon 4p connected to the predetermined second semiconductor layer 2 in the region where the porous silicon region P1 is to be formed is used as the positive electrodes E1 and E2 for anodizing treatment. Then, the back side of the second semiconductor layer 2 is brought into contact with the electrolytic solution, and a predetermined voltage is applied between the negative platinum electrode G in the electrolytic solution. As a result, current flows between the positive electrodes E1 and E2 made of the selected buried polycrystalline silicon 4p and the negative platinum electrode G, and silicon around the current path is partially melted and anodized. A porous silicon region P1 reaching the buried insulating film 3 can be formed. Note that the porous silicon region P1 may be oxidized after the formation of the porous silicon region P1.

  Thus, the semiconductor device 20 shown in FIG. 1 can be manufactured.

  As described above, according to the above method, the porous silicon region P1 can be easily formed only by adding the anodizing process to the normal device forming process, and the semiconductor device 20 of FIG. It can be manufactured at low cost. In addition, according to the manufacturing method shown in FIG. 3, it is possible to omit the formation of the back electrode on the semiconductor substrate 11 as the positive electrode for the anodizing treatment. it can.

  FIG. 4 is a schematic cross-sectional view of a semiconductor device 23 as a modification of the semiconductor device 20 shown in FIG.

  Also in the semiconductor device 23 shown in FIG. 4, as in the semiconductor device 20 shown in FIG. 1, the porous silicon region P <b> 4 is formed in the second semiconductor layer 2 on the back surface side of the SOI structure semiconductor substrate 12. 2 is separated into two field regions F7 and F8. On the other hand, the porous silicon region P4 in the semiconductor device 23 of FIG. 4 is different from the porous silicon region P1 in the semiconductor device 20 shown in FIG. It has a structure extending over the entire surface. As a result, the entire back surface side of the semiconductor substrate 12 can be protected by the porous silicon region P4e extending in the surface layer portion. For this reason, for example, even when the field regions F7 and F8 are fixed to different reference potentials, they can be easily mounted on a lead frame or the like.

  For the purpose of protecting the back side of the semiconductor substrate and facilitating mounting on the lead frame or the like, an insulating film such as a silicon oxide film may be formed on the entire back side of the semiconductor device. . In addition, when moisture absorption of the porous silicon region becomes a problem, a change in characteristics due to moisture absorption of the semiconductor device can be prevented by forming a silicon nitride film that does not allow moisture to pass through the entire back surface.

  FIGS. 5A and 5B are diagrams for explaining a method of manufacturing the semiconductor device 23 shown in FIG. 4, and are schematic cross-sectional views of the semiconductor device 23 being manufactured.

  As shown in FIGS. 5A and 5B, when the semiconductor device 23 of FIG. 4 is manufactured, the anodizing treatment is performed in two steps. In the step shown in FIG. 5A, all the buried polycrystalline silicon 4p of the insulating isolation trench 4 formed in the first semiconductor layer 1 is used as the positive electrodes E1 to E6 of the anodizing treatment, and the second semiconductor is used. A porous silicon region P4e is formed over the entire surface of the surface layer on the back side of the layer 2. In the step shown in FIG. 5B, the second semiconductor layer 2 is formed by using the predetermined buried polycrystalline silicon 4p in the region where the porous silicon region P4 is to be formed as the positive electrodes E1 and E2 for anodizing treatment. A porous silicon region P4 that is separated into two field regions F7 and F8 is formed.

  Thereby, the semiconductor device 23 of FIG. 4 can be manufactured. Note that the order of the steps shown in FIGS. 5A and 5B may be reversed.

  FIG. 6 is a schematic cross-sectional view of the semiconductor device 24 as another example of the semiconductor device.

  In each of the semiconductor devices 20 to 23 described above, the polycrystalline silicon 4p of the insulating isolation trench 4 connected to the second semiconductor layer 2 is an electrode for fixing the potential of the field regions F1 to F8 of the second semiconductor layer 2. It was used for. On the other hand, in the semiconductor device 24 shown in FIG. 6, the dedicated electrode 5 is formed on the back surface side of the second semiconductor layer 2 in the semiconductor substrate 13, and the second semiconductor layer 2 separated by the porous silicon region P5. The potentials of the field regions F9 and F10 are fixed by the electrode 5 on the back surface side. As shown in FIG. 6, the potential is fixed by mounting the semiconductor device 24 on the lead frame LF and electrically connecting the corresponding electrode 5 and the lead frame LF. As described above, a dedicated electrode may be formed on the back surface side of the second semiconductor layer 2 to fix the potential of each field region separated by the porous silicon region.

  FIG. 7 is a diagram for explaining a method of manufacturing the semiconductor device 24 shown in FIG. 6, and is a schematic cross-sectional view of the semiconductor device 24 being manufactured.

  As shown in FIG. 7, a resist mask M1 having an opening H1 in the region where the porous silicon region P5 is to be formed is formed on the back surface side of the semiconductor substrate 13, and the previously formed electrode 5 is subjected to anodization. A porous silicon region P5 is formed by using it as an electrode.

  Thus, the semiconductor device 24 shown in FIG. 6 can be manufactured.

  Even in the case of the manufacturing method using the buried polycrystalline silicon on the main surface side as the positive electrode for anodizing treatment, a resist mask having an opening in the region where the porous silicon region is to be formed is provided on the back side of the semiconductor substrate. Alternatively, the porous silicon region may be selectively formed.

  As described above, in each of the semiconductor devices, the low potential reference circuit portion and the high potential reference circuit portion are provided in the first semiconductor layer on the main surface side of the SOI structure semiconductor substrate having the buried insulating film 3. Even if there is a steep fluctuation of the reference potential in the high-potential reference circuit section in a small semiconductor device, the influence (potential interference) on the surrounding device formation region can be suppressed, resulting in malfunction. A difficult semiconductor device can be obtained.

  Therefore, the above semiconductor device requires a low potential reference circuit portion and a high potential reference circuit portion, and is suitable for a high voltage IC for driving an inverter in which these circuit portions are formed on one semiconductor substrate for miniaturization. is there. In particular, it is suitable as an in-vehicle semiconductor device that needs to handle a high voltage of several hundred volts to several hundreds of volts.

1 is a schematic cross-sectional view of a semiconductor device 20 as an example of the semiconductor device of the present invention. (A), (b) is a schematic bottom view of the semiconductor devices 21 and 22, respectively, which is the same semiconductor device as the semiconductor device 20 shown in FIG. It is typical sectional drawing of the semiconductor device 20 in the middle of manufacture using anodization. FIG. 5 is a schematic cross-sectional view of a semiconductor device 23 as a modification of the semiconductor device 20 shown in FIG. 1. (A), (b) is a figure explaining the manufacturing method of the semiconductor device 23 shown in FIG. 4, and is typical sectional drawing of the semiconductor device 23 in the middle of manufacture, respectively. FIG. 4 is a schematic cross-sectional view of a semiconductor device 24 as another example of a semiconductor device. It is a figure explaining the manufacturing method of the semiconductor device 24 shown in FIG. 6, and is typical sectional drawing of the semiconductor device 24 in the middle of manufacture. It is a typical example of a conventional high voltage IC for driving an inverter, and is a schematic top view of a high voltage IC90. It is a typical example of a conventional high voltage IC for driving an inverter, and is a schematic cross-sectional view of a high voltage IC 90.

Explanation of symbols

20-24,90 Semiconductor device (high voltage IC)
10 to 13 (SOI structure) semiconductor substrate 1 first semiconductor layer (SOI layer)
2 Second semiconductor layer (support substrate)
3 buried insulating film 4 insulating isolation trench 4s sidewall oxide film 4p buried polycrystalline silicon D device formation region P1 to P5 porous silicon region F1 to F10 field region

Claims (11)

In an SOI structure semiconductor substrate composed of a first semiconductor layer made of silicon on the main surface side and a second semiconductor layer made of silicon on the back surface side with a buried insulating film interposed therebetween,
A low potential reference circuit portion and a high potential reference circuit portion are provided in the first semiconductor layer on the main surface side,
Each of the device formation regions in the low potential reference circuit portion and the high potential reference circuit portion is a semiconductor device that is insulated and isolated from each other by an insulation isolation trench that reaches the buried insulating film,
A porous silicon region that is more porous than the second semiconductor layer is formed in the second semiconductor layer on the back side so as to reach the buried insulating film,
Partitioned by the porous silicon region, the second semiconductor layer is separated into a plurality of field regions;
A semiconductor device characterized in that the field region is fixed in potential. The field region immediately below the high potential reference circuit unit is fixed at the same reference potential as the high potential reference circuit unit,
2. The semiconductor device according to claim 1, wherein the field region immediately below the low potential reference circuit unit is fixed to the same ground (GND) reference potential as that of the low potential reference circuit unit. The insulating isolation trench is an insulating isolation trench made of a sidewall oxide film and buried polycrystalline silicon;
The buried polycrystalline silicon is connected to the field region through the buried insulating film;
3. The semiconductor device according to claim 1, wherein the potential of the field region is fixed from the main surface side of the semiconductor substrate through the buried polycrystalline silicon.   4. The semiconductor device according to claim 1, wherein the porous silicon region is extended over the entire surface of the back surface layer portion of the second semiconductor layer. 5.   The semiconductor device according to claim 1, wherein the porous silicon region is oxidized.   The semiconductor device according to claim 1, wherein the semiconductor device is a high-voltage IC for driving an inverter.   The semiconductor device according to claim 1, wherein the semiconductor device is for vehicle use. In an SOI structure semiconductor substrate composed of a first semiconductor layer made of silicon on the main surface side and a second semiconductor layer made of silicon on the back surface side with a buried insulating film interposed therebetween,
A low potential reference circuit portion and a high potential reference circuit portion are provided in the first semiconductor layer on the main surface side,
Each device formation region in the low potential reference circuit portion and the high potential reference circuit portion is insulated from each other by an insulation isolation trench reaching the buried insulating film,
A porous silicon region that is more porous than the second semiconductor layer is formed in the second semiconductor layer on the back side so as to reach the buried insulating film,
Partitioned by the porous silicon region, the second semiconductor layer is separated into a plurality of field regions;
The field region is a method of manufacturing a semiconductor device in which a potential is fixed,
A method of manufacturing a semiconductor device, wherein the porous silicon region is formed by anodization. The insulating isolation trench is an insulating isolation trench made of a sidewall oxide film and buried polycrystalline silicon;
The insulating isolation trench is formed in advance so that the buried polycrystalline silicon is connected to the second semiconductor layer through the buried insulating film,
9. The semiconductor device according to claim 8, wherein the porous silicon region is formed by anodization using the predetermined buried polycrystalline silicon connected to the second semiconductor layer as a positive electrode. Production method. The anodization is performed in a two-stage process,
10. The method of manufacturing a semiconductor device according to claim 8, wherein the porous silicon region extends over the entire surface of the back surface side surface portion of the second semiconductor layer. 11.   The method for manufacturing a semiconductor device according to claim 8, wherein the porous silicon region is oxidized.

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