JPS6022828B2 - Manufacturing method of semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device including a semiconductor element with high density and suitable for high speed operation.

An active element with a novel structure according to the present invention is an example of an IC.
The transistor has the following characteristics.

That is, [11] The area occupied by a unit transistor can be reduced to 1/3 to 1/10 of the area occupied by a transistor manufactured by conventional manufacturing techniques.

'21 Since the transistor occupies a very small area, parasitic capacitance effects can be reduced, and in particular, base-collector junction capacitance can be reduced to 1/3 to 1/10 in transistors with this structure compared to conventional transistors.

Glue The manufacturing process technology required to form a transistor with this structure can be sufficiently formed at the conventional technology level.

As mentioned above, in an IC incorporating a transistor having the structure according to the present invention, the degree of integration can be improved compared to conventional methods by using multilayer electrode wiring technology that makes full use of microfabrication technology, transfer element separation technology, etc. It can be improved to about 1.

Furthermore, the parasitic capacitance is extremely small, allowing for ultra-high-speed logic operation.
It can also serve as an ultra-high frequency operating IC. Next, before explaining the manufacturing method of the present invention, a method for manufacturing a transistor as a related example will be described with reference to the drawings for comparison.

Figure 1 (Formation of separation region and collector lead-out region on base)
The base body is formed by forming an N-type epitaxial layer 3 on a substrate 1 of P conductivity type with an N-type buried layer 2a interposed therebetween, and the main surface thereof is covered with an insulating coating 4 of Sj02.

P is applied to the epitaxial layer using the insulating film as a mask.
A type impurity is selectively diffused to form an isolation region la connected to the substrate 1, and then an N-type impurity is selectively diffused by changing the opening of the insulating film and connected to the embedded layer 2a, and a collector is formed between this and the insulating layer 2a. A collector lead-out region 2b forming region 2 is provided. FIG. 2 (Formation of Base Region) A hole is opened in the insulating film at a portion where the base region is to be formed, and a P-type impurity is diffused to form the base region 5.

Note that the exposed surface of the formed base region is covered with an insulating film 4' of Si02. FIG. 3 (Formation of emitter region) Openings are provided in the portion of the insulating film 4' on the base region where the emitter region is to be formed and a part of the collector lead-out region, and N-type impurities are diffused through the openings to form the emitter region 6 and the collector lead-out region. A collector contact region 2c is formed.

FIG. 4 (Formation of electrodes in each region) Openings for leading out the collector, base, and emitter regions are provided in the insulating film, a metal layer is deposited, and ohmic connections are made to the respective regions in the openings, Each is patterned into a predetermined shape, and the collector electrode 12
, a base electrode 15, and an emitter region 16 are formed.

In the conventional transistor of the above example, the area S occupied by the unit transistor separated by the isolation region is determined by the masking accuracy (base shape,
This cannot be reduced because it depends on the patterning accuracy of the electrode metal layer, etc.).

In other words, it is impossible to reduce the parasitic capacitance effect due to the large occupied area, and the I
There was a strong need for improvement in order to improve the performance of C. The present invention provides a manufacturing method that meets the demand for improvements to the conventional semiconductor device manufacturing method.

This invention can reduce the base-collector junction capacitance in an example of a transistor, and can significantly reduce the area occupied by a unit transistor in an IC, thereby improving electrical characteristics such as ultra-high-speed logic operation and ultra-high frequency operation. Achieve improvements, etc.

Next, the present invention will be explained in detail with reference to drawings showing a part of the manufacturing process in order of a method of manufacturing a semiconductor device according to an embodiment.

Figure 5 (Formation of separation region and collector lead-out region on base)
A first insulating film 24 of Si02 is deposited on the exposed main surface of a substrate 1 having a P conductivity type and an N-type epitaxial base layer 23 formed thereon with an N-type buried layer 28 interposed therebetween.

Then, using the insulating film as a mask, a P-type impurity is selectively diffused into the epitaxial layer through the barrier holes to form the substrate 1.
A collector lead-out region 2b is formed which connects to the buried layer 2a and forms a collector region 2 together with the buried layer 2a by selectively diffusing N-type impurities by changing the barrier of the insulating film. is provided. Figure 6
After a second insulating film 34 of doped oxide is deposited on the first insulating film 24, both insulating films 2 are deposited on the portion where the base region is to be formed by photoetching.
4 and 34 are provided with continuous openings 20.

FIG. 7 (Formation of base region forming layer) An N-type silicon epitaxial layer 25 is deposited on the second insulating film including the barrier holes.

This is a vapor phase growth, and the portion grown on the exposed surface of the N-type epitaxial layer 23 in the opening becomes the single crystal silicon layer 25s, and the portion grown on the second insulating film 34 becomes the polycrystalline silicon layer 25p. Therefore, they can grow at the same time. Actually, it is formed by thermal decomposition of silane (Si ratio) at a substrate temperature of 950° C. or higher, or by hydrogen reduction reaction of tetrachlorosilane (Sic14) at a substrate temperature of 1100° C. or higher. Furthermore, the level difference around the dark hole based on the film thickness of both the laminated insulating films (5000 A as an example) is such that when the N-type epitaxial base layer 23 has a crystal orientation <100>, the single crystal silicon layer is compared to the polycrystal silicon layer. The exposed surface of the epitaxial layer 25 is formed flat by using advantageously the difference in the growth rate in which the growth rate is dominant (however, when the crystal orientation is <111>, the respective growth rates are not much in phase with each other). This is easy, and the flat exposed surface makes it possible to perform fine photo etching in several steps later. Next, heating is applied to form a base region to diffuse P-type impurities contained in the doped oxide. 25s' is a single crystal silicon layer, and 25p' is a polycrystalline silicon layer.

FIG. 8 (Formation of base region) The epitaxial layer is patterned by photoetching and then covered with a third insulating film 44. FIG.

FIG. 9 (Formation of emitter region) A hole is formed in the part of the third insulating film where the emitter region is planned to be formed, and a hole is formed in the part where the collector contact region with the first insulating film 24 or the second insulating film 24 is planned to be formed. Holes are provided respectively, and N-type impurities are highly diffused through the holes to form respective diffusion regions.

In the figure, 26 is an emitter region, and 2c is a collector contact region. FIG. 10 (Formation of electrodes in each region) Openings for leading out each region of the collector region 2c, base region 25s', and emitter region 26 are formed in the third insulating film 44, the first without, and the second. Insulating coating 24, 34
A metal layer is applied to each hole to make an ohmic connection to each region, each of which is patterned into a predetermined shape, and has a collector potential 12 and a base electrode 3.
5. Form emitter electrode 36.

The transistors formed by the method of the present invention in some ICs as described above are compared with the transistors formed by the conventional method and are shown in cross-sectional view in FIG.

That is, the transistor shown in the upper part of FIG. 11 is the same as that shown in FIG. 4 by the conventional method, and the transistor shown in the lower part is the same as that shown in FIG. The correspondence is shown below. First, according to this invention, the dimensions required for the base area &
may be selected to include the dimension E2 necessary for the emitter region, taking into account the photomask alignment margin dimension.

For example, when the emitter dimension E2 is formed to 2mm, there is a remarkable advantage that the base dimension & can be reduced to about 4 to 6mm. On the other hand, when using the follow-up method, the emitter region dimension E and the base region dimension B must be set sufficiently wide in order to form a wiring electrode pattern. The method of the present invention for achieving the above consists of a single crystal silicon layer region whose base region forms an effective base region, and a polycrystalline silicon layer region from which said region is derived, and whose base region forms a part of the collector region. Based on a special structure in which only the effective base area is connected to the pitaxial base layer and the rest is electrically insulated by an insulating film (first insulating film), the emitter is The area occupied by a unit transistor can be changed from S to S2 (S, > S2) without changing the spacing between the electrode and base electrode.
can be reduced to Further, the present invention achieves this invention by doping the polycrystalline silicon layer 25p' connected to the base region using the doped oxide layer 34 as a diffusion source to form a guide layer for leading out the base electrode with lower resistivity. has significant advantages. Furthermore, the doped oxide layer 34 (second
(insulating film) is used to cover the polycrystalline silicon layer 25p' with the silicon oxide 24 (first insulating film) in the collector region 2.
It is effective in achieving good electrical isolation from 3. Next, since the area occupied by the emitter region outside the transistor according to the present invention is the same as that of a transistor having a conventional structure, the current capacity that can be passed through the transistor can also be maintained at the same level.

Furthermore, as described above, since the base-collector junction capacitance can be significantly reduced, a transistor with a high cutoff frequency h can be manufactured. Furthermore, the area occupied by the unit transistor itself can be reduced by the reduction in the area of the base region, and has very significant advantages such as high-density and high-speed change in element performance.

[Brief explanation of the drawing]

FIGS. 1 to 4 are conventional sectional views, FIGS. 5 to 10 are cross-sectional views showing a part of the manufacturing process according to an embodiment of the present invention, and FIG. FIG. 3 is a cross-sectional view showing a comparison of structures of transistors produced by manufacturing methods of Examples. Note that the same reference numerals in each figure indicate the same or corresponding parts. la... Separation area, 2...
... Collector region, 2a ... Collector buried layer, 2b ... Collector region deriving layer, 3, 23 ...
...N-type epitaxial base layer, 24...First insulating film, 25'...Epitaxial layer for forming base region, 25s'...Silicon single crystal, 25p
'...Silicon polycrystal, 26...Emitter region, 34...Second insulating film, 44...
...Third insulation film. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11

Claims (1)

[Claims] 1. A first insulating film and a second insulating film containing impurities of a second conductivity type are laminated on one exposed principal surface of a first conductivity type vapor-grown single crystal silicon base layer which is a part of a silicon substrate and serves as a collector region. a step of providing an opening corresponding to the planar shape of a desired effective base region communicating with both of the insulating coatings of the portion where the base region is to be formed; and a step of forming a vapor-grown layer on the insulating coating including the opening. forming a single crystal silicon layer in contact with the opening and a polycrystalline silicon layer in contact with the insulating film, respectively; and diffusing and introducing impurities of a second insulating film into the vapor growth layer. A step of forming the polycrystalline silicon layer into a desired pattern shape by using the formed single crystal silicon layer as a base region of a transistor and further including the polycrystalline silicon layer which becomes a base region leading conductive layer; a step of covering the growth layer with a third insulating film; a step of opening a hole in the third insulating film at a portion where the third insulating film contacts the effective base region and diffusing a first conductivity type impurity to form an emitter region; manufacturing a semiconductor device comprising the step of forming an electrode in a region where the third insulating film contacts an emitter region and a base region leading conductive layer, and a region where the first insulating film contacts a collector region, respectively; Method.