JPS6027193B2 - semiconductor circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in a semiconductor circuit device having MOS transistors as constituent elements.

As the degree of integration of MOS-LSI increases, it has been required to shorten the channel length (distance between source and drain) of MOS transistors, which are the constituent units, but as a result, punch-through phenomenon short-channel effects on the value voltage (extremely high when the channel length is short,
(effect of lowering the value voltage) and lowering the drain breakdown voltage. Conventionally, in order to prevent the short channel effect of the threshold voltage and the decrease in drain breakdown voltage due to such punch-through phenomenon, it was considered to increase the impurity concentration of the entire substrate (lower the specific resistance). This method increases the substrate constant k (a coefficient representing the amount of change in voltage that is appropriate for the voltage between the source and the substrate), which is undesirable in terms of LSI configuration.

In particular, since the threshold voltage of the load MOS transistor changes greatly, the load characteristics deteriorate significantly. The threshold of the load MOS transistor of the commonly used E-○ (enhancement reduction) type MOS-IC,
The load characteristics when the value voltage is 1.5V (power supply voltage = 2.5V) vary greatly depending on the value of the substrate constant k, as shown in the load characteristics diagram of the conventional MOS transistor in Figure 1, and k≧ 1, the characteristics are worse than those of a resistive load.
This invention ~ Punch Q when the channel length becomes short
The object of the present invention is to provide a semiconductor circuit device which suppresses the through phenomenon and whose load characteristics as a load MOS transistor do not become worse than those of a resistive load even if the substrate constant k of the MOS transistor becomes large.

The present invention will be explained below with reference to Examples. FIG. 2 is a longitudinal sectional view of the main part of an embodiment in which the present invention is applied to an N-channel MOS transistor.

In the figure, a P-type silicon substrate with a specific resistance of 10 to 15Q is formed on one main surface of the P-type silicon substrate by epitaxial growth, ion implantation, or impurity diffusion, and has a specific resistance of 2 to 40. 3 is an N-type or N-type layer h formed to a thickness of about 10 mm on the P+ type layer 2 by ion implantation or impurity diffusion; 4 is an N-
5 is a gate insulating film made of a silicon dioxide (Si02) film deposited on the surface of the N-type or N-type layer 3 to form a predetermined channel layer and provided with a thickness of about 500 to 1000 A. Polycrystalline silicon layers 6 and 7 are formed by vapor phase growth on 4, sandwiching the N-type or N-type layer 3 under the gate insulating film 4, and forming an N-type or N-type layer 3.
These are N0 type source and drain regions provided to reach the P00 type layer 2 from the surface of the type layer 3. Next, the characteristics of the MOS transistor according to the present invention will be described.

3 and 4 are load characteristic diagrams of the MOS transistor of the above embodiment.
．． In the case of 5V, FIG. 4 shows the characteristics when the value voltage is -4V.

In the conventional MOS transistor, as shown in Figure 1,
When the substrate constant k increases (specific resistance decreases), the equivalent load resistance decreases rapidly, and the substrate constant k becomes i. 0(
Specific resistance of P type substrate is 50mm, thickness of gate oxide film is 1000mm
(equivalent to case A), the characteristics are already inferior to those of a resistive load. On the other hand, the characteristics of the MOS transistor according to the present invention, which has a negative threshold voltage and a large absolute value, are as follows.
As shown in the figure, even if K increases to 1.5 (corresponding to the case where the specific resistance of the P 10 layer is 20℃ and the gate oxide film thickness is 1000△), the characteristics are still better than those of the resistive load. I keep it.
Moreover, in the MOS transistor of the present invention shown in FIG. 2, in order to reduce the substrate constant k, an eaves-shaped silicon substrate of 10 to 150 types and a high-competitive type are used.
P+ layer 2 to 2 to 48 to prevent punch through.
Since the arc and the specific resistance are low, even if the substrate constant k becomes large, the threshold voltage has the opposite polarity to the power supply voltage and its absolute value can be greater than the absolute value of the drain voltage, and the dependent It has become possible to create a M○S transistor for loads that is superior to resistive loads.In the MOS transistor according to the present invention, the substrate constant k is small because the specific resistance of the semiconductor substrate is high ~ Moreover, the threshold voltage is low, so the same area Since it becomes possible to flow a large amount of drain current, the channel width required to flow the same amount of drain current can be narrowed.
Also, by providing a low resistivity semiconductor layer between the semiconductor substrate and the source and drain regions, it is possible to prevent punch Q-through and shorten the channel length to about 1 m, making it possible to further increase the Next, a method for manufacturing the MOS transistor of the embodiment shown in FIG. 2 will be described.

First, as shown in Figure 5a, the specific resistance 1
0 to 150 on a P-type silicon substrate 1 by epitaxial growth, ion implantation, or impurity diffusion.
A P+ layer 2 having a specific resistance of 2 to 40 m is formed to a thickness of 145 to 2.0 mm.

Next, as shown in FIG. 5b, an N-type or N-type layer 3 is formed on the P layer 2 to a thickness of about 1.0 m by ion implantation or impurity diffusion. , as shown in FIG.
2. A polycrystalline silicon layer 5 is formed on the top surface of the film by vapor phase epitaxy, and as shown in FIG.
The remaining polycrystalline silicon layer is removed except for necessary portions such as the gate electrode portion. Next remaining polycrystalline silicon layer 5
As shown in FIG. 5e, the Si02 film 4 is
A gate insulating film 4 is formed by etching. At the same time as phosphorus is diffused to increase the electrical conductivity of the polycrystalline silicon layer 5 of the gate electrode, a source region 6 and a drain region 7, which are N-shaped mirrors, are formed as shown in FIG. 5f. The following polycrystalline silicon layer 5, source region 6, drain region 7
The formation of the SiQ film covering the SiO2 film, the formation of contact holes in this SiO2 film, the formation of electrodes in the contact hole portions, etc. are the same as in the case of conventional MOS transistors, so detailed explanations will be omitted. Although the above description has been made regarding N-channel MOS transistors, the present invention can be similarly applied to P-type channel MOS transistors.

Furthermore, it goes without saying that the present invention can be applied to all MOSs having the above-mentioned MOS transistors as constituent elements. As detailed above, the semiconductor circuit according to the present invention includes a P-type (or N-type) high-resistivity semiconductor substrate and a low-resistivity P+-type (or N+-type) semiconductor substrate provided on the semiconductor substrate. a first semiconductor layer and an N-type or N-type (
or P-type or P-type) second semiconductor layer; N+ type (or P-type) source and drain regions are provided in the regions leading to the drain voltage, and the threshold voltage has the opposite polarity to the drain voltage and its absolute value is greater than or equal to the absolute value of the drain voltage. Since the component is a MOS transistor characterized by the following, even if the substrate constant of the MOS transistor becomes large, the load characteristics as a load MOS transistor do not become worse than in the case of a resistive load.

Also, this MOS transistor has a high specific resistance of the semiconductor substrate, so the substrate constant k is small and the threshold voltage is low, so it is possible to flow a large amount of drain current in the same area, and it is possible to flow the same amount of drain current. The channel width required for
Since punch-through can be prevented and the channel length can be shortened, it has the effect of making it possible to integrate poems.

[Brief explanation of drawings]

Figure 1 is a load characteristic diagram of a conventional load MOS transistor.
FIG. 2 is a vertical cross-sectional view of a MOS transistor constituting an embodiment of the present invention, FIGS. 3 and 4 are load characteristic diagrams of the MOS transistor of the embodiment as a load transistor, and FIG. 1 is a vertical cross-sectional view of the main manufacturing steps of the MOS transistor of the example. In the figure, the silicon substrate (semiconductor substrate) 2 is a P-type layer (first semiconductor layer), 3 is an N-type or N-type layer (contains a second semiconductor layer), 4 is a gate insulating film, and 5 is a gate insulating film. A polycrystalline silicon layer (gate electrode), 6 is an N+ type source region, and 7 is an N+ type drain region. Note that the same reference numerals in the figures indicate the same or corresponding parts, respectively. Figure 4 Figure 5

Claims (1)

[Claims] 1. A P-type (or N-type) semiconductor substrate, a P^+-type (or N^+-type) first semiconductor layer formed on this semiconductor substrate, and this first semiconductor layer. A semiconductor substrate comprising a second semiconductor layer of N^-type or N-type (or P^-type or P-type) formed thereon; N^+ type (or P^+ type) source and drain regions formed in regions extending into the first semiconductor layer across the channel region, and coating the surface of the channel region of the semiconductor substrate; and a gate electrode formed on the gate insulating film, the threshold voltage is of opposite polarity to the drain voltage and its absolute value is greater than or equal to the absolute value of the drain voltage. A semiconductor circuit device that uses MOS transistors as a component. 2. The semiconductor circuit device according to claim 1, wherein the semiconductor substrate has a specific resistance of 10 to 15 Ωcm, and the first semiconductor layer has a specific resistance of 2 to 4 Ωcm. 3. The semiconductor circuit device according to claim 2, wherein the first semiconductor layer has a thickness of 1.5 to 2.0 μm. 4. The semiconductor circuit device according to claim 1, wherein the second semiconductor layer has a thickness of approximately 1 μm.