JPS6110990B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an insulated gate field effect transistor, and an object of the present invention is to increase the breakdown voltage.

Insulated gate field effect transistors are widely used because they have features such as high input resistance, good cross-modulation characteristics, and ease of integration. However, insulated gate field effect transistors generally have a lower breakdown voltage than bipolar transistors, and their ability to handle high voltages is extremely limited. The causes are: (1) Electric field concentration tends to occur on the drain junction surface.

(2) If the channel length is short, punch-through is likely to occur between the source and drain.

(3) If the gate insulating film is thin, dielectric breakdown is likely to occur between the gate and drain.

Things like that. Various efforts have been made to eliminate these causes.

For example, (1) create a structure in which the gate electrode does not overlap the drain region (offset gate structure), (2) increase the thickness of the insulating film under the gate electrode near the drain, (3) create a second insulating film near the drain. providing a gate electrode of
(Stack gate structure) methods have been devised. However, even with these efforts, it has only been possible to achieve a withstand voltage of about 400V at most.

The present invention provides a novel structure that increases the withstand voltage as a whole by dividing the gate region into a part that controls current according to the input and several parts that maintain the drain voltage, and furthermore, each of the parts. The present invention provides an insulated gate field effect transistor with a new structure that increases the withstand voltage and improves stability during operation. The operation and structure will be specifically described below with reference to the drawings. Here, a description will be given using a metal-silicon oxide film-silicon (MOS) transistor as an example.

FIG. 1 shows an example of the structure of an n-channel MOS transistor in an embodiment of the present invention. The figure shows half a cross-section of a circular structure with center line AA'. In this example, a case will be explained in which there are two n-type intermediate regions, which will be described later. However, the present invention is not limited to this, and the number of intermediate regions may be increased. In the figure, 01 is a p-type silicon substrate, 11, 12, 13, 14 are
N-type regions selectively formed in the p-type substrate, 21, 22, and 23 are gate oxide films, and 31, 3 are gate oxide films, respectively.
2 and 33 indicate gate electrodes. Gate electrodes 32, 33 make resistive contact with n-type regions 12, 13. Source region 11 and drain region 1
4, a voltage as shown in the figure is applied by an external power supply 41 through a load resistor 61. 51 and 52 indicate input and output terminals, respectively. No drain voltage is applied to the substrate surface under the gate oxide films 22, 23, and the electrodes 32,
When 33 is at the same potential as the substrate, an n-type inversion layer is formed (depression type).

It has been found that an element with this structure operates as follows when the dimensions of each region, the impurity concentration of the substrate, etc. satisfy the conditions described later.

In the device shown in Fig. 1, when a voltage that does not cause an n-type inversion layer to form under the gate oxide film 21 is applied to the input terminal 51 (cut-off state) and the drain voltage is increased, a current flows between the source and drain. First, almost all the voltage applied between the source and drain appears between the source 11 and the region 13,
This state continues until the potential of region 13 rises to a value close to the voltage at which the n-type inversion layer under gate oxide film 23 disappears due to the back gate bias effect (referred to as V _TBG ). During this time, region 12 and region 13 are at almost the same potential. When the drain voltage is further increased, the potential of region 13 remains at approximately V _TBG , and any increase in voltage beyond that
and the drain 14, and a depletion layer from the drain extends toward the region 13.
When this depletion layer reaches the region 13 (punch through), the rate of increase in the potential difference between the drain 14 and the region 13 becomes small, and the potential of the region 12 remains approximately at the potential of V _TBG , and the potential of the region 13 The potential of is rising. Similarly, as the drain voltage is increased, the depletion layer extends from region 13 to region 12, and until there is punch-through between regions 13 and 12, the increase in drain voltage occurs mostly between this region. This is covered by the increase in potential difference at . When punching through between regions 13 and 12, the potential of region 12 begins to rise above V _TBG ,
The depletion layer from region 12 to source 11 further expands.

On the other hand, a voltage is applied to the input terminal 51 to generate an n-type inversion layer under the gate oxide film 21 (conducting state).
As the drain voltage is increased, the potential of region 13 remains at a value smaller than V _TBG , and regions 12 and 13
The potential settles down to a state where an n-type inversion layer sufficient to conduct the same current is formed under the gate oxide films 21, 22, and 23. The increase in the potential of the region 13 is caused by the increase in the potential of the region 13.
determined by the potential applied to and the threshold voltage of the portion below the gate oxide films 22, 23.
If the drain voltage remains at a value smaller than V _TBG and increases beyond that level, a depletion layer will grow from the drain 14 to the region 13, and the operation will be similar to that in the cut-off state.

In this way, the factors that determine the overall withstand voltage between the source and drain in the structure shown in Figure 1 are (1) the punch-through voltage at which the depletion layer spreads throughout the source and drain, and (2) the breakdown voltage of the drain junction itself. By increasing the number of intermediate n-type regions, the overall breakdown voltage can be increased to approximately the breakdown voltage of the drain junction itself.

However, as can be seen from the explanation of the operation described above, several conditions such as the following are required in order to perform such an operation.

(1) In the cut-off state, the potential rise in the intermediate n-type region that is not punched through is kept at V _TBG ,
Furthermore, in order to reduce the potential drop between the source and drain in the conductive state, the electrodes 32 and 33
The lower part must form a depletion type MOS transistor.

(2) The punch-through voltage between the source 11 and the region 12, the dielectric strength voltage between the region 12 and the input gate electrode 31, and the breakdown voltage of the junction of the region 12 must be greater than V _TBG .

(3) Between areas 12 and 13 or area 13
and drain 14, the punch-through voltage must be less than the breakdown voltage of each junction and the dielectric strength voltage between its source-proximal gate electrode and each intermediate region or drain.

In order to satisfy these conditions (1), (2), and (3), the plane orientation and resistivity of the substrate, the thickness of the gate oxide film, the material and dimensions of the gate electrode, and the distance between the n-type regions must be adjusted appropriately. must be chosen. These choices are
In the case of the structure shown in FIG. 1, the following procedure is performed, for example.

First, the gate electrode material, the thickness of the gate oxide film,
Assuming the gate oxide film formation method, the impurity concentration and surface orientation of the substrate, the threshold voltage at which an inversion layer is generated under the gate oxide film is determined, and it is confirmed that a depletion type MOS transistor is formed. Next, find the back gate bias voltage V _TBG necessary to erase this inversion layer, and calculate this V _TBG
is smaller than the breakdown voltage of the junction and the dielectric strength voltage of the gate oxide film. In this case, the normal breakdown voltage of the junction needs to be slightly modified to take into account the electric field concentration near the surface that is unique to MOS transistors. Furthermore, the width of the depletion layer at V _TBG is determined, and the distance between the source and the first intermediate region is determined to be larger than this width. Next, find the width of the depletion layer at the smaller of the dielectric strength voltage of the gate oxide film or the breakdown voltage of the junction, and calculate the distance between the intermediate regions and between the intermediate region and the drain as follows: The punch-through voltage is determined by setting the distance to be smaller than the depletion layer width. Furthermore, the number of intermediate regions for realizing a desired operating voltage is determined as the sum of the punch-through voltages. The MOS transistor section below the input gate may be either an enhancement type or a depletion type depending on the usage conditions.

An example of the structure and manufacturing method of an actual device made by following such a design procedure will be explained with reference to FIG. The device shown in FIG. 2 has a gate electrode structure slightly different from that shown in FIG. 1 in order to alleviate the limitations caused by the dielectric breakdown voltage of the gate oxide film, but the basic design concept is the same. FIG. 2 shows a case where the intermediate area has three stages. FIG. 2 shows half of a cross-section of the circular structure centered on the line AA'. Here, 01 is high resistivity p-type silicon, 1
1, 12, 13, 14, 15 are n-type regions made by selective diffusion of impurities in p-type silicon, 2
1, 22, 23, 24 are gate oxide films, 31, 3
2, 33, 34, 35 are polycrystalline silicon with n-type impurity diffused, 41, 42, 43, 44 are polycrystalline silicon with no impurity diffused, 51, 5
2 and 55 are metals (for example, aluminum) for taking out the electrodes. Polycrystalline silicon 32, 33, 34, and 35 with n-type impurities diffused therein make resistive contact with n-type regions 12, 13, 14, and 15, respectively, and the relationship between each n-type diffusion region and polycrystalline silicon is become the same potential. The spacing between each diffusion layer is 50μ
For example, in polycrystalline silicon 33 with n-type impurities diffused, each n-type polycrystalline silicon protrudes from the n-type intermediate diffusion region to the top of the gate oxide film on both sides. They protrude above 22 and 23 by 10μ and 20μ, respectively.

To create this structure, the following steps are taken. First, a thermal oxide film of about 5000 Å is grown on a p-type (111) plane silicon wafer of about 100 Ω·cm. Next, the oxide film on the portion that will become the actual transistor is removed by photolithography. Next, a thermal oxide film of approximately 2000 Å is grown in this region in a humid oxygen atmosphere at 900° C., and the oxide film in the portion that will become the n-type diffusion region is removed again by photolithography. On top of this, polycrystalline silicon is grown over the entire surface, for example, by thermal decomposition of monosilane.
The polycrystalline silicon on the outside of 1 is removed by photolithography, and then the gate oxide film protruding outside of 31 is removed using the polycrystalline silicon as a mask. Furthermore, the upper portions of 41, 42, 43, and 44 are covered with a material that acts as a mask against impurity diffusion (for example, a silicon oxide film grown by reacting monosilane in an oxygen atmosphere). An n-type impurity is diffused over the entire surface from above, and then the electrodes 51, 5
2,55, the structure of FIG. 2 is realized. With this structure, by using region 11 as the source, region 15 as the drain, and n-type polysilicon 31 as the input gate electrode, a MOS transistor with a withstand voltage of 500 V or more, which was previously unobtainable, was realized.

As shown in FIG. 2, making the n-type polycrystalline silicon that makes resistive contact with each n-type intermediate region protrude above the gate oxide film on the source side of the n-type region is a process that This greatly contributes to increasing the breakdown voltage of the area, and in the structure shown in Figure 1, the
The withstand voltage, which was only around 70V, was able to be increased to over 100V. As a result, we were able to achieve a withstand voltage of 800V when the intermediate region had four stages.

Also, when creating the structure shown in Figure 2, polycrystalline silicon parts (41, 42, 43,
Although a substantially similar structure can be obtained by removing n-type impurities after removing 44), in this case, unstable conditions such as fluctuations in characteristics were exhibited during operation. This instability was eliminated by leaving undoped polycrystalline silicon between each region, as shown in FIG. This is because polysilicon, which has a resistivity of about 10 ⁶ Ω·cm and does not diffuse impurities, masks external influences. In particular, when a passivation layer such as a silicon nitride film is applied over the entire polycrystalline silicon, it has been shown to be extremely stable against external influences.

The structure shown in the present invention is an enhancement type
The so-called E/DMOS integrated circuit, which uses a MOS transistor as a drive element and a depletion type MOS transistor as a load element, can be manufactured with almost no changes to the process. An output device can be realized with a single board.

As described above, the present invention allows the gate region to
It is divided into a part that controls the current according to the input, and a part that consists of multiple parts that maintains the drain voltage.
The present invention provides an insulated gate field effect transistor with a novel structure that achieves high withstand voltage, and has the advantage of not only increasing the withstand voltage but also improving stability during operation.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing the principle of the present invention, and FIG. 2 is a sectional view of an insulated gate field effect transistor according to an embodiment of the present invention. 01... Semiconductor substrate, 11... Source region, 1
2 to 14... intermediate region, 15... drain region,
21-24...Gate insulating film, 31-35...Polycrystalline silicon doped with impurities, 41-44...
...polycrystalline silicon that is not doped with impurities,
51, 52, 55...Metal for taking out the electrode.

Claims (1)

[Scope of Claims] 1. A semiconductor substrate of one conductivity type has a substrate and a source region/drain region of the opposite conductivity type formed in isolation, and a source region/drain region is provided between the source region and the drain region. has a plurality of intermediate regions of the same conductivity type as the source region, a gate insulating film formed on the surface between the source region, each intermediate region, and the drain region; A film including a gate electrode is formed only on the gate insulating film that covers the surface of the region, covering the entire surface or a part thereof to form an input transistor, and the entire surface or a part of the gate insulating film excluding the input transistor is used as the source of the gate insulating film. It is covered with a film including an intermediate gate electrode that makes resistive contact with the intermediate region closer to the drain, and the area under this gate insulating film has depletion type characteristics, and the withstand voltage of the input transistor is set between each intermediate region and between the intermediate region closest to the drain. The potential change in the intermediate region is set to be greater than or equal to the amount of potential change in the intermediate region necessary for the plurality of intermediate transistors formed between the drain regions to enter the cut-off state, and the punch-through voltage of the intermediate transistor is set to An insulated gate field effect transistor characterized by having a breakdown voltage lower than a breakdown voltage and a breakdown voltage between an intermediate region and an electrode near its source. 2. Claim 1, characterized in that a part of the film formed on the gate insulating film and including the gate electrode or the intermediate gate electrode is a semi-insulating film.
The insulated gate field effect transistor described in . 3. Claim No. 3 characterized in that the intermediate gate electrode making resistive contact with each intermediate region and the electrode making resistive contact with the drain region extend onto the gate insulating film near the source region of each of the regions. The insulated gate field effect transistor according to item 1 or 2. 4. Claim 2, characterized in that the gate electrode and the intermediate gate electrode are polycrystalline silicon in which impurities of the same conductivity type as the source and drain regions are diffused, and the semi-insulating film is polycrystalline silicon in which impurities are not diffused. The insulated gate field effect transistor according to item 1 or 3.