JPS58132958A - Integrated capacitance - Google Patents

Abstract

PURPOSE:To suppress change of capacitance within a wide positive and negative voltage range by providing, in addition to a second electrode in the same conductive type as an accumulation layer, a third electrode in the same conductivity type as an inversion layer in such a manner as in contact with said inversion layer and by using the second and third electrodes in common as the one electrode. CONSTITUTION:A thin silicon oxide layer 2 is formed on an N type substrate 1 and a first electrode 3 is then formed on said silicon oxide film 2, and a second electrode 5 of N<+> layer and a third electrode 6 of P type diffusion layer are provided in the substrate 1. Thereby, a P type inversion layer 4 generated when a negative voltage is applied to the electrode 3 is connected to the electrode 6 and thereby a capacitance CO is formed between the electrodes 3 and 6. Accordingly, a capacitance between the common electrode connecting the electrodes 5 and 6 and the electrode 3 changes in only a small amount.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the structure of an integrated capacitor in a semiconductor integrated circuit.

An object of the present invention is to provide an integrated capacitor whose capacitance value is constant over a wide operating voltage range.

A detailed explanation will be given below based on the drawings. FIG. 1 is a cross-sectional view showing the structure of a basic integrated capacitor in an integrated circuit, in which a thin silicon oxide layer 2 is formed on an N-type substrate 1 as a dielectric layer. A first electrode 6 made of a conductive material is provided thereon, and a second N layer is provided in the N type substrate 1.
electrodes 5 are provided. This type of capacitor is called MO8 capacitor.

It is well known that the capacitance value of the MO8 capacitor having the structure shown in FIG. 1 has voltage dependence, and its characteristics are as shown by the solid line in the characteristic diagram of FIG.

That is, when the voltage applied to the first electrode 6 is in the positive direction with the second electrode 5 as a reference, the capacitance value shows the value of Co;
When a negative voltage is applied to the first electrode 6, a certain voltage V
The capacitance value begins to decrease from x, and the rate at which the voltage decreases from Vy becomes smaller.

The above phenomenon is explained by the generation of a depletion layer on the surface of the N-type substrate 1. In FIG. 1, when a positive voltage is applied to the first electrode 6, an N accumulation layer is formed near the surface of the N type substrate 1, but this N accumulation layer is simply connected to the second electrode. The conductivity of the first electrode 6 and the N-type substrate 10 is not related to the capacitance value.
Value of capacitance (first capacitance) between the surface and the surface C8
appears directly.

On the other hand, when a negative voltage is applied to the first electrode 6, electrons are driven away near the surface of the N-type substrate 10, creating a depletion layer without carriers. This depletion layer is connected in series to the first capacitor C8 as a second capacitor having a value of C7, so that the overall capacitance value is lower than C1. When a larger negative voltage is applied, a P-type inversion layer 4 begins to form on the surface of the N-type substrate 1 as shown in the cross-sectional view of FIG. layer 10
is formed at the junction between the P-type inversion layer 4 and the N-type substrate 1. When the negative voltage applied to the first electrode B is further increased, most of the applied electric field is
It is used to increase the thickness of the type inversion layer 4, and since the thickness of the depletion layer 10 does not increase that much,
7, there is no change, and therefore the overall capacitance value change is small.

When using a capacitor as described above, there is no problem as long as only a positive voltage is applied to the first electrode B, since the capacitance value will always be constant.

However, under usage conditions in which voltages in both positive and negative directions are applied to the first electrode B, the capacitance value changes depending on the voltage, which is not preferable. Therefore, a capacitor whose capacitance value does not change depending on the voltage is required.

As mentioned above, the capacitance value changes because the second capacitor C5 is connected in series with the first capacitor C1.
If the capacitance C7 is made sufficiently large, the change in capacitance value will be small.

Incidentally, the second capacitance value C2 becomes smaller as the thickness of the depletion layer 10 becomes thinner. Depletion layer 1D in semiconductor
The thickness becomes thinner as the impurity concentration increases. Therefore, as shown in the cross-sectional view of FIG. The thickness of the depletion layer formed at the junction surface of the layer with the second electrode 5a becomes thinner, the value of the second capacitance C1 becomes larger, and the voltage at which the P-type inversion layer is formed also becomes smaller. The characteristics are improved as shown by the broken line in the characteristic diagram of FIG.

However, if the negative voltage applied to the first electrode B is further increased, the thickness of the P-type inversion layer 4 becomes larger and larger, and eventually exceeds the second electrode 5a of the N layer. Then, the thickness of the depletion layer between the P-type inversion layer 4 and the N-type substrate 1 increases, and the overall capacitance value decreases again. The above problem can be avoided if the second electrode 5a of the N layer is provided deep enough, but usually the second electrode 5a of the N layer is formed at the same time in the manufacturing process of the drain or source electrode of another transistor. It is difficult to make it deep enough.

Another object of the present invention is to solve the above-mentioned problems, and to provide a capacitor with excellent characteristics without adding any special steps.

FIG. 5 is a cross-sectional view showing the structure of an integrated capacitor according to the first embodiment of the present invention. An electrode 6 is provided. In this way, the P-type inversion layer 4 that is generated when a negative voltage is applied across the first electrode is connected to the third electrode 6, so that the Even if the capacitance decreases, a capacitance C8 is created between the first electrode 3 and the third electrode 6. Therefore, by connecting the second electrode 5 and the third electrode 6 in common and looking at the capacitance between them and the first electrode 6, the characteristics are improved as shown by the solid line in the characteristic diagram of FIG. Ru.

FIG. 7 is a cross-sectional view showing the structure of a β-concentrating capacitor according to a second embodiment of the present invention, in which the characteristics shown in FIG.
The capacitance value change in a relatively low voltage region is made smaller and more stable, and at the same time as the third electrode 6 is provided in the N-type substrate 1 as shown in FIG. 3
A second N layer is formed under the silicon oxide layer 2 corresponding to the position of
This shows the case where the electrode 5b is expanded. The characteristics in this case are shown by broken lines in FIG.

FIG. 8 shows a third embodiment of the present invention, in which the third electrode 6a is spread under the silicon oxide layer 2 corresponding to the position of the first electrode 3, contrary to the case of FIG. 7 is a cross-sectional view showing the structure of a capacitor, the characteristics of which are the opposite signs of the characteristics shown by the broken line in FIG. 6. FIG. However, in this case,
Since the storage layer is P type and the inversion layer is N type, it is better to consider the P type electrode as the second electrode and the N type electrode as the third electrode.

FIG. 9 is a sectional view showing the structure of an integrated capacitor according to a fourth embodiment of the present invention, in which a second electrode 5C and a third electrode 6
b is spread under the silicon oxide layer 2 corresponding to the position of the first electrode layer, and its characteristics are symmetrical as shown in the characteristic diagram in Figure 10, so it may be used depending on the purpose of use. Easy capacity.

As is clear from the above embodiments, the first gist of the present invention is that the second and third electrodes are provided in the MO8 capacitor at a position where it can be connected to a second inversion layer of the same type as the storage layer. By using one electrode in common, it is possible to provide an integrated capacitor whose capacitance value changes little over a wide positive and negative voltage range.

Next, FIGS. 11(a) and 11(b) are a plan view and a sectional view showing the structure of an integrated capacitor according to a fifth embodiment of the present invention, which is a further improvement of the first to fourth embodiments. That's what I did. That is, in the first to fourth embodiments described above, when the inversion layer 4 is formed, this inversion layer 4 is used as a conductor, but the inversion layer 4 generally has a large resistance value, and therefore, the voltage is particularly high. In a low region, the Q value of the capacitance decreases. Therefore, the reversal layer 4 is connected to the third wage level (
Or the third electrode 6a or 6. It is better to connect it with b). Therefore, as shown in FIGS. 11('a) and (b), for example, both the second electrode 5d and the third electrode 6c are shaped like comb teeth,
If the inversion layer 4 is arranged so as to penetrate into each other, the inversion layer 4 can come into contact with the third electrode 6 over a very short distance, so that the Q value of the capacitance increases significantly. Note that, for convenience of drawing, the plan view of FIG. 11(b) is shown with the silicon oxide layer 2 and the first electrode 3 omitted.

That is, the second gist of the present invention is based on the first gist, but by providing at least the third electrode in a comb-like shape on a plane, the Q value is high and can be applied over a wide positive and negative voltage range. The purpose is to provide an integrated capacitor with little change in capacitance value.

As described above, according to the present invention, an integrated capacitor with a small change in capacitance value and a high Q value can be obtained with respect to both positive and negative voltages, and its effects are very large. In the above description, the substrate is of N type, but it is a matter of course that the same type of implementation can be performed even if the substrate is of P type. Further, as shown in FIGS. 9 and 11, there are cases where the roles of the second electrode and the third electrode are not clear, and they work complementary to each other.

Further, in the above description, the second and third electrodes are used in common, but the two electrodes may be used independently.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing the structure of a conventional MO8 type integrated capacitor. FIG. 2 is a characteristic diagram of the capacitance shown in FIG. Figure 3 explains the drawbacks of the capacity shown in Figure 1. FIG. FIG. 4 is a sectional view showing the structure of another conventional MO8 type integrated capacitor. FIG. 5, FIG. 7, FIG. 8, and FIG. 9 are sectional views showing the structure of MO8 type integrated capacitors according to each embodiment of the present invention. FIG. 6 is a characteristic diagram showing the male characteristics of each example shown in FIGS. 5 and 7, FIG. 10 is a characteristic diagram showing the characteristics of the example shown in FIG. 9, and FIGS. FIG. 11(b) is a plan view and a sectional view showing the structure of a MOS type integrated capacitor which is still another embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... N-type substrate, 2... Silicon oxide layer, 6... First electrode, 4... Inversion layer, 5.5a, 5b, , 5c, 5d-...=second electrode layer, 6.6a, 6b, 6c......third electrode layer
-7do+iTADA

Claims (3)

[Claims] (1) In an MO8 integrated capacitor in which an oxide film provided on the surface of a semiconductor substrate is used as a dielectric and a conductive material provided on the oxide film is used as a first electrode, a second electrode of the same type as the storage layer is used. An integrated capacitor characterized in that, in addition to the electrode, a third electrode of the same type as the inversion layer is provided so as to be able to contact the inversion layer. (2) The integrated capacitor according to claim 1, wherein the second electrode and the third electrode are commonly connected. (3) The integrated capacitor according to claim 1, characterized in that the third electrode is placed in comb-like contact with the inversion layer.