JPS6034819B2 - Storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a one-transistor memory device using a V-MOS configured in the order of source, base, and drain from the surface.

A cross-sectional structural diagram of a conventional example is shown in FIG. 1a, and its equivalent circuit diagram is shown in FIG. 1b.

As the charge storage amount Cs for information storage, the junction capacitance between the p-na type substrate 1 and the n-type source region 2 is used, and as a switch element, the drain region 3, base region 4, V-MOS configured in the darkness of source area 2
Transistor Tr (power transistor: T.J.Rod
Hoko r Setal. lEEEJ. SC-9, No. 5, P
．． 239, Cct. 1974) is used.
Note that 5 is a silicon oxide film, 6 is an aluminum electrode, and 7 is a silicon oxide film.
indicates a V-shaped groove. The V-shaped groove 7 (notch) is formed by selective etching with surface index dependence, and when the surface opening width of the V-shaped groove 7 is W, the depth D is approximately D 0.7.
There is a certain relationship called W.

In this conventional example, a bare-shaped source region 2 is formed in the lowest layer from the surface, and in order to operate the V-MOS transistor Tr normally, the depth of the V-shaped groove 7 is set to the n-shaped source region 2. Since the surface opening width W must be widened, the surface opening width W must be widened. That is, the planar dimensions of the element are limited by the depth of the V-shaped groove 7. The distance between the surface and the n+ type source region 2 is the depth Dn+ of the diffusion layer of the n+ type drain region 3, the thickness Dn+ of the wedge-shaped base layer 4' in the base region 4, and the p+ type base layer. 4″ thickness D
It is the sum of p0, and when determining the withstand voltage of the element, the thickness D<0> of this may not be able to be made thinner than a certain value. Therefore, the planar dimensions are limited independently of the element miniaturization technology, which is disadvantageous for element miniaturization. In addition, a junction capacitor is used as the charge storage capacitor C3, but as is well known, the amount of stored charge Q and the voltage Vc at both ends have a nonlinear relationship, and V8 of approximately Q (0<n<
1).

For example, in the case of a stepped joint, n=1/2, and in the case of a straight slope joint, n=2'3. Therefore, the voltage required to store the same amount of charge is higher than that of an ordinary linear capacitor, for example, a capacitor formed of polysilicon, Si02, n+ layer. voltage is required. This invention has been made in view of the above points.

This invention will be explained below. A cross-sectional structural diagram of one embodiment of the basic element of the present invention is shown in FIG. 2a, and an equivalent circuit diagram thereof is shown in FIG. 2b. The switch element includes a source region 12, a base region 13 (a region where a channel is formed in the exposed portion of the V-shaped groove), and a drain region 14 in this order from the surface of the substrate 11. The breakdown voltage of the device can be made sufficiently large by making the high resistance drain region 14' sufficiently thick among the high resistance drain region 14' and the low resistance drain region 14'' that constitute the drain region 14. 1a, the depth of the V-shaped groove 20 only needs to slightly exceed the boundary between the base region 13 and the drain region 14, so the depth of the V-shaped groove 20 depends on the thickness of the drain region 134. In other words, the planar dimensions of the element can be made smaller than the conventional structure with the same breakdown voltage.Furthermore, as the charge storage capacitor CS, the source region 12 and the Si02 film 15 thereon are used as the charge storage capacitor CS. A capacitance formed between the four polysilicon layers 16 formed through the capacitance is used, and unlike a junction capacitance, this is a linear capacitance, that is, QMVc, so the voltage for charge storage is also the same as in Figure 1. It may be smaller than that of the conventional one, and is advantageous for miniaturization.

Note that 17 is an aluminum gate electrode, 18 is an aluminum drain region, and 19 is a contact layer.

FIGS. 3a, 3b, and 3c show a planar pattern diagram and a sectional structural diagram of a storage device using the configuration shown in FIG. 2.

In these figures, 21 is an aluminum electrode of the polysilicon layer 16, and 18' and 21' are contact holes. n-type low resistance drain region 14'', n
The type high-resistance drain regions 14' can be sequentially formed in the p-type substrate 11 using, for example, ion implantation.

The p+ type base region 13 and the n+ type source region 12 can be formed by epitaxial growth, ion implantation, or impurity diffusion. Other components such as the V-shaped groove 20, the polysilicon film 16, the Si02 film 15, and the aluminum wiring can be easily formed using conventional techniques, and there are no particular difficulties in manufacturing this device. In the conventional example shown in FIG. 1, the area that mainly contributes to the miniaturization of device dimensions is the area of the elongated source region 2 inside the semiconductor, but in the present invention, it is the area of the n+ type source region 12 on the surface. In either case, miniaturization of the dimensions is required.

In the conventional example, the n0-type source region 2 is formed at an early stage of the manufacturing process, and then the base region 4 is formed and a thermal process is performed to form the n0-type drain region 3. In each case, the source region 2 increases due to thermal diffusion of impurities. This is a disadvantage in miniaturizing the area. In contrast, in the present invention, since the source region 12 is present on the surface, the source region 12 can be formed in the final thermal step, and the above-mentioned drawbacks are significantly alleviated. As described above, according to the present invention, since the part that contributes to the miniaturization of device dimensions is the source region on the surface, it can be formed in the last manufacturing process, and therefore changes due to thermal diffusion of impurities caused by multiple processes can be avoided. It has the advantage of being extremely suitable for miniaturization.

[Brief explanation of the drawing]

Figures 1a and 1b are a cross-sectional structural diagram of a conventional example and its equivalent circuit diagram,
Figures 2a and 2b are cross-sectional structural diagrams and equivalent circuit diagrams of one embodiment of the present invention, and Figures 3a, b, and c are planar patterns of a storage device using the configuration shown in Figure 2. Figure, its X-X
They are a cross-sectional view taken along a line and a cross-sectional view taken along a Y-Y line. In the figure, 11 is a substrate, 12 is a source region, 13 is a base region, 14 is a drain region, 15 is an Sj02 film, 16 is a polysilicon layer, 17 is a gate electrode, 18 is a drain electrode, 19 is a contact layer, and 20 is a V-shaped structure, 21 is an electrode. Figure 1 Figure 2 Figure 3 Figure 3

Claims (1)

[Claims] 1. A first semiconductor region of a second conductivity type, which is an opposite conductivity type to the first conductivity type, formed at a certain depth in a semiconductor substrate of a first conductivity type, and a first semiconductor region in contact with the first semiconductor region. a second semiconductor region of a first conductivity type formed so as to partially extend into the semiconductor substrate; and a second semiconductor region of a second conductivity type formed in the second semiconductor region separately from the first semiconductor region. a first highly conductive thin film formed on the third semiconductor region via an insulating film; and a first conductive thin film formed from the surface of the third semiconductor region, and the first semiconductor region and the second semiconductor region a second highly conductive thin film formed via the insulating film on the surface of the second semiconductor region exposed on the surface of the V-shaped groove having a depth exceeding the boundary of , a capacitor constituted by the first highly conductive thin film and the third semiconductor region is used as a charge storage means, the first semiconductor region is a drain region, the second semiconductor region is a channel forming region,
A memory device characterized in that a unit memory section is constructed by using a field effect transistor as a switch element, with the third semiconductor region serving as a source region and the second highly conductive thin film serving as a gate electrode.