JPS6329421B2 - - Google Patents
Info
- Publication number
- JPS6329421B2 JPS6329421B2 JP57214518A JP21451882A JPS6329421B2 JP S6329421 B2 JPS6329421 B2 JP S6329421B2 JP 57214518 A JP57214518 A JP 57214518A JP 21451882 A JP21451882 A JP 21451882A JP S6329421 B2 JPS6329421 B2 JP S6329421B2
- Authority
- JP
- Japan
- Prior art keywords
- terminal
- control gate
- electrode
- semiconductor substrate
- conductivity type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000000758 substrate Substances 0.000 claims description 16
- 239000004065 semiconductor Substances 0.000 claims description 11
- 229910052710 silicon Inorganic materials 0.000 description 10
- 239000010703 silicon Substances 0.000 description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 239000002184 metal Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000012535 impurity Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/92—Capacitors with potential-jump barrier or surface barrier
- H01L29/93—Variable capacitance diodes, e.g. varactors
Description
【発明の詳細な説明】
本発明は容量変化率を任意に制御し得る可変容
量ダイオードに関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a variable capacitance diode whose capacitance change rate can be arbitrarily controlled.
従来、半導体基板内に形成されたPN接合に外
部制御電圧を印加し、この電圧によつてPN接合
部に形成される容量が変化することを利用した可
変容量ダイオードはバリキヤツプと呼ばれ広く利
用されている。その可変容量ダイオードの代表的
な例を第１図乃至第２図について説明する。第１
図は従来公知の可変容量ダイオードの構造で、低
抵抗のシリコン基板１の表面に高抵抗のシリコン
層２が形成され、このシリコン層２の表面に不純
物の選択拡散によつてリング状あるいはライン状
の基板に対し逆導電型の高不純物濃度層３，４が
作られる。この３及び４と２との間にPN接合
５，６が形成される。それぞれの領域に７，８，
９，１０で示す電極が設けられている。この電極
７，８はP+層３，４に逆バイアス電圧を印加す
るためのコントロールゲート端子で、電極９が容
量変化を読み出すための読み出し端子である。又
電極１０は共通端子で、１２は基板表面に設けら
れた絶縁物層である。 Conventionally, variable capacitance diodes, which utilize the fact that an external control voltage is applied to a PN junction formed in a semiconductor substrate and the capacitance formed at the PN junction changes depending on this voltage, are called varicaps and have been widely used. ing. Typical examples of the variable capacitance diode will be explained with reference to FIGS. 1 and 2. 1st
The figure shows the structure of a conventionally known variable capacitance diode, in which a high resistance silicon layer 2 is formed on the surface of a low resistance silicon substrate 1, and a ring or line shape is formed on the surface of this silicon layer 2 by selective diffusion of impurities. High impurity concentration layers 3 and 4 of opposite conductivity type are formed on the substrate. PN junctions 5 and 6 are formed between these 3 and 4 and 2. 7, 8, in each area
Electrodes shown at 9 and 10 are provided. The electrodes 7 and 8 are control gate terminals for applying a reverse bias voltage to the P + layers 3 and 4, and the electrode 9 is a read terminal for reading capacitance changes. Further, the electrode 10 is a common terminal, and the reference numeral 12 is an insulating layer provided on the surface of the substrate.
次に、図に示された可変容量ダイオードの動作
について説明する。コントロールゲート端子７，
８と共通端子１０間に逆バイアス電圧を印加して
シリコン層２中に空乏層１１を広げ、読み出し端
子９と共通端子１０との間の容量を変化させる。
コントロールゲート端子７，８と共通端子１０と
の間の電圧（以下CG電圧と略す）と読み出し端
子９と共通端子１０との間の容量（以下Ｒ容量と
略す）との関係を代表的なものについて示すと第
２図の通りである。図に示すようにCG電圧に対
してＲ容量が変わるので、この部分を利用して可
変容量ダイオードとして利用する。この制御電圧
と容量との特性は半導体基板の比抵抗等で決めら
れ固定されたものであつた。従つて、第２図に示
す容量変化率のゆるやかなダイオードあるいは急
激に変化するダイオードを得る場合には個々に所
定の半導体基板にダイオードを作る必要がある。
一般に第１図に示した公知の可変容量ダイオード
の特性は急激なものであつて、ゆるやかな容量変
化率の可変容量ダイオードを得るのは難かしく、
それだけ回路設計に制約を与えている。 Next, the operation of the variable capacitance diode shown in the figure will be explained. control gate terminal 7,
A reverse bias voltage is applied between the read terminal 8 and the common terminal 10 to expand the depletion layer 11 in the silicon layer 2 and change the capacitance between the read terminal 9 and the common terminal 10.
A typical relationship between the voltage between the control gate terminals 7 and 8 and the common terminal 10 (hereinafter abbreviated as CG voltage) and the capacitance between the readout terminal 9 and the common terminal 10 (hereinafter abbreviated as R capacitance) This is shown in Figure 2. As shown in the figure, the R capacitance changes with respect to the CG voltage, so this portion is used as a variable capacitance diode. The characteristics of this control voltage and capacitance were determined and fixed by the resistivity of the semiconductor substrate and the like. Therefore, in order to obtain a diode with a gradual capacitance change rate or a diode with a rapid change rate as shown in FIG. 2, it is necessary to fabricate each diode on a predetermined semiconductor substrate.
In general, the characteristics of the known variable capacitance diode shown in FIG. 1 are abrupt, and it is difficult to obtain a variable capacitance diode with a gradual rate of change in capacitance.
This places restrictions on circuit design.
そこで、本発明の目的は容量変化率を任意に制
御可能にした可変容量ダイオードを提供するに在
る。 Therefore, an object of the present invention is to provide a variable capacitance diode whose capacitance change rate can be controlled arbitrarily.
本発明は上記目的を達成するため、第１導電型
の半導体基板と、該半導体基板の一方の表面上に
形成された共通電極と、上記半導体基板の他方の
表面上に列状に並設された複数の島状第２導電型
領域と、上記各第２導電型領域の長手方向両端部
に形成された第１及び第２制御電極と、上記第
１、第２制御電極に夫々接続された第１、第２端
子と、上記半導体基板の他方の表面において上記
島状第２導電型領域に挟まれた部分に形成された
読出し電極と、を備え、上記第１端子と第２端子
とに夫々独立にバイアス電圧を印加することによ
り上記共通電極と読出し電極との間で読出される
容量値を制御するように構成したことを特徴とす
る。 In order to achieve the above object, the present invention includes a semiconductor substrate of a first conductivity type, a common electrode formed on one surface of the semiconductor substrate, and a common electrode arranged in a row on the other surface of the semiconductor substrate. a plurality of island-shaped second conductivity type regions, first and second control electrodes formed at both ends in the longitudinal direction of each of the second conductivity type regions, and connected to the first and second control electrodes, respectively. first and second terminals; and a readout electrode formed on the other surface of the semiconductor substrate at a portion sandwiched between the island-shaped second conductivity type regions; The present invention is characterized in that the capacitance value read between the common electrode and the read electrode is controlled by applying bias voltages to each independently.
以下、本発明の一実施例について説明する。 An embodiment of the present invention will be described below.
第３図乃至第４図は発明に係わる可変容量ダイ
オードの上面図及びＡ−Ａ部の縦断面図である。
本実施例に於いては二つのコントロール電極を設
けて容量変化率を制御するものである。図に於い
て、１は低抵抗N+型シリコン基板で、２はその
表面に作られた高抵抗Ｎ型シリコン層である。こ
の層の所定領域にＰ型不純物の拡散によつて作ら
れた島状のP+領域３、４が在る。シリコン層２
の表面は絶縁物層１２で被われているが、一部に
P+領域３、４の長手方向両端部に該領域とのコ
ンタクト用の孔が作られそれぞれ電極金属層１
３，１４，１５，１６が設けられている。電極金
属層１３，１４は共通に接続され第１のコントロ
ールゲート電極となり、１５，１６も又共通に接
続されて第２のコントロールゲート電極となる。
尚、電極金属９と１０は読み出し端子、共通端子
である。１１は第１及び第２のコントロールゲー
ト端子に外部制御用電圧を印加することによつて
シリコン層２中に広がつた空乏層１１を示してい
る。図の場合第１のコントロールゲート電極に印
加された電圧が第２コントロールゲート電極に印
加した電圧より高い場合を示している。 3 and 4 are a top view and a longitudinal cross-sectional view taken along line A-A of the variable capacitance diode according to the invention.
In this embodiment, two control electrodes are provided to control the capacitance change rate. In the figure, 1 is a low-resistance N + type silicon substrate, and 2 is a high-resistance N-type silicon layer formed on its surface. In predetermined regions of this layer, island-shaped P + regions 3 and 4 are formed by diffusion of P type impurities. silicon layer 2
The surface of is covered with an insulating layer 12, but some parts
Holes for contact with the P + regions 3 and 4 are formed at both longitudinal ends of the electrode metal layer 1, respectively.
3, 14, 15, and 16 are provided. Electrode metal layers 13 and 14 are connected in common to form a first control gate electrode, and electrode metal layers 15 and 16 are also connected in common to form a second control gate electrode.
Note that the electrode metals 9 and 10 are read terminals and common terminals. Reference numeral 11 indicates a depletion layer 11 that is expanded in the silicon layer 2 by applying an external control voltage to the first and second control gate terminals. The figure shows a case where the voltage applied to the first control gate electrode is higher than the voltage applied to the second control gate electrode.
空乏層の広がりは、PN接合の逆バイアス電圧
によつて決まるので第１コントロールゲートと第
２コントロールゲートの電位をそれぞれ共通端子
に対して任意に設定すれば、読み出し電極で読み
出される容量は任意にコントロールできることに
なる。特に第２コントロールゲート電位を共通端
子１０と同一にし、第１コントロールゲート電位
を共通端子１０に対して負にすれば第１コントロ
ールゲート付近の空乏層は大きく広がり、第２コ
ントロールゲート付近の空乏層は広がらない。こ
の時第１コントロールゲート電位をさらに負方向
に大きくすれば読み出し電極下の絶縁膜直下にま
で空乏層は広がるが、第２コントロールゲート付
近では空乏層は広がらないので読み出し電極から
読み出される容量の変化はさほど急激にはならな
い。このようにして、従来の三端子可変容量ダイ
オードの欠点である急激な容量変化を防ぐことが
できる。又、第１コントロールゲートと第２コン
トロールゲート電位を独立に設定することによ
り、容量変化の割合（容量変化率）を自由に選ぶ
ことができる。 The spread of the depletion layer is determined by the reverse bias voltage of the PN junction, so if the potentials of the first control gate and the second control gate are set arbitrarily with respect to the common terminal, the capacitance read out by the readout electrode can be arbitrarily set. You will be able to control it. In particular, if the second control gate potential is made the same as that of the common terminal 10 and the first control gate potential is made negative with respect to the common terminal 10, the depletion layer near the first control gate expands greatly, and the depletion layer near the second control gate does not spread. At this time, if the first control gate potential is further increased in the negative direction, the depletion layer will expand to just below the insulating film under the readout electrode, but the depletion layer will not expand near the second control gate, so the capacitance read from the readout electrode will change. It won't be that sudden. In this way, rapid capacitance changes, which are a drawback of conventional three-terminal variable capacitance diodes, can be prevented. Further, by setting the first control gate potential and the second control gate potential independently, the rate of capacitance change (capacitance change rate) can be freely selected.
尚、両コントロールゲート電位を同一にすれば
従来の三端子可変容量ダイオードと同じものがで
きる。 Note that if both control gate potentials are made the same, the same as a conventional three-terminal variable capacitance diode can be obtained.
以上、本発明の実施例から明らかな通り、可変
容量ダイオードの容量変化率を、外部印加電圧に
よつて任意に設定できるため、急激な容量変化を
避けることができ、同調回路等の設計の余裕度を
増すことができる。 As is clear from the embodiments of the present invention, the capacitance change rate of the variable capacitance diode can be set arbitrarily by the externally applied voltage. You can increase the degree.
本発明は上述した実施例に限定されず、本発明
は本発明の要旨から逸脱しない範囲から種々変更
し得る。例えば、コントロールゲート端子を２端
子について説明したが、３端子にして更にきめこ
まかく容量変化率を調整することも可能である。 The present invention is not limited to the embodiments described above, and the present invention may be modified in various ways without departing from the gist of the present invention. For example, although the description has been made using two control gate terminals, it is also possible to use three terminals to more finely adjust the capacitance change rate.
第１図は公知の可変容量ダイオードの縦断面
図、第２図は従来の可変容量ダイオードの特性
図、第３図は本発明に係わる可変容量ダイオード
の上面図、第４図は第３図のＡ−A′部縦断面図
である。
１……N+型シリコン基板、２……Ｎ型シリコ
ン層、９……読み出し端子、１０……共通端子、
１１……空乏層、１３，１４……第１コントロー
ルゲート端子、１５，１６……第２コントロール
ゲート端子。
FIG. 1 is a longitudinal sectional view of a known variable capacitance diode, FIG. 2 is a characteristic diagram of a conventional variable capacitance diode, FIG. 3 is a top view of a variable capacitance diode according to the present invention, and FIG. 4 is a diagram similar to that of FIG. It is a longitudinal cross-sectional view taken along the line A-A'. 1... N + type silicon substrate, 2... N type silicon layer, 9... Read terminal, 10... Common terminal,
11... Depletion layer, 13, 14... First control gate terminal, 15, 16... Second control gate terminal.
Claims (1)
電極と、 上記半導体基板の他方の表面上に列状に並設さ
れた複数の島状第２導電型領域と、上記各第２導
電型領域の長手方向両端部に形成された第１及び
第２制御電極と、 上記第１、第２制御電極に夫々接続された第
１、第２端子と、 上記半導体基板の他方の表面において上記島状
第２導電型領域に挟まれた部分に形成された読出
し電極と、を備え、 上記第１端子と第２端子とに夫々独立にバイア
ス電圧を印加することにより上記共通電極と読出
し電極との間で読出される容量値を制御するよう
に構成したことを特徴とする可変容量装置。[Claims] 1. A semiconductor substrate of a first conductivity type, a common electrode formed on one surface of the semiconductor substrate, and a plurality of common electrodes arranged in a row on the other surface of the semiconductor substrate. an island-like second conductivity type region, first and second control electrodes formed at both ends in the longitudinal direction of each of the second conductivity type regions, and a first control electrode connected to the first and second control electrodes, respectively. a second terminal; and a readout electrode formed on the other surface of the semiconductor substrate at a portion sandwiched between the island-like second conductivity type regions, and the first terminal and the second terminal are independently connected to each other. A variable capacitance device characterized in that the capacitance value read between the common electrode and the readout electrode is controlled by applying a bias voltage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21451882A JPS59104180A (en) | 1982-12-06 | 1982-12-06 | Variable capacity diode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21451882A JPS59104180A (en) | 1982-12-06 | 1982-12-06 | Variable capacity diode |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59104180A JPS59104180A (en) | 1984-06-15 |
| JPS6329421B2 true JPS6329421B2 (en) | 1988-06-14 |
Family
ID=16657045
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21451882A Granted JPS59104180A (en) | 1982-12-06 | 1982-12-06 | Variable capacity diode |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59104180A (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61289659A (en) * | 1985-06-18 | 1986-12-19 | Fuji Photo Film Co Ltd | Solid-state image pickup device |
| JPS61288986A (en) * | 1985-06-18 | 1986-12-19 | 株式会社 サンエス商工 | Joint for robot |
| US5220194A (en) * | 1989-11-27 | 1993-06-15 | Motorola, Inc. | Tunable capacitor with RF-DC isolation |
| JPH10319864A (en) * | 1997-05-09 | 1998-12-04 | Internatl Business Mach Corp <Ibm> | Mounting structure for display device and equipment provided with the same |
| SE515783C2 (en) * | 1997-09-11 | 2001-10-08 | Ericsson Telefon Ab L M | Electrical devices and process for their manufacture |
| JP4046634B2 (en) | 2003-04-08 | 2008-02-13 | Ｎｅｃエレクトロニクス株式会社 | Voltage-controlled capacitance element and semiconductor integrated circuit |
-
1982
- 1982-12-06 JP JP21451882A patent/JPS59104180A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59104180A (en) | 1984-06-15 |
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