JPS6328347B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a variable capacitance device having three terminals, which is designed to reduce the chip size.

The structure shown in Fig. 1 is an example of a three-terminal variable capacitance device configured to separately provide a depletion layer control electrode for controlling the extension of the depletion layer and a capacitance readout electrode for reading the capacitance change due to the depletion layer. It has been known. In the same figure, 1 is the N ⁺ type layer, and 2 is this layer.
N type layer formed on N ⁺ type layer 1, 3 is N type layer 2
4 is a ^PN junction, 5 is an insulating film, 6 is a depletion layer control electrode provided on the P ⁺ type layer 3, and 7 is provided on the insulating film 5. A capacitance readout electrode 8 is a common electrode for both electrodes 6 and 7 provided on the N ⁺ type layer 1. In the above, when a reverse bias voltage is applied between the depletion layer control electrode 6 and the common electrode 8, the PN junction 4
Since the depletion layer 9 mainly expands toward the N-type layer 2 side where the impurity concentration is low, the capacitance readout electrode 7 and the common electrode 8
A change in capacitance occurs between the capacitance and the capacitance readout electrode 7, and a capacitance change corresponding to a change in reverse bias voltage is read out from the capacitance reading electrode 7. Compared to the conventional two-terminal variable capacitance device configured to serve as both the depletion layer control electrode and the capacitance readout electrode, such a three-terminal variable capacitance device can achieve a steep capacitance change in response to a change in reverse bias voltage. It has the advantage of being

However, as mentioned above, the impurity concentration of the N-type layer 2 for expanding the depletion layer 9 is usually 10 ¹⁴ /cm ³
However, with this value, it is necessary to set the spacing between the P ⁺ type layers 3 to several μ in order to obtain the desired capacitance change.
If it is desired to increase the capacitance read out between the capacitance readout electrode 7 and the capacitance readout electrode 7, a large number of the P ⁺ type layers 3 must be provided as shown in FIG. This P ⁺ type layer 3
Since the width of the depletion layer control section including the depletion layer control electrode 6 is required to be a value of 10 to 20 microns, most of the area of the semiconductor chip is occupied by the depletion layer control section including the depletion layer control electrode 6. It becomes difficult to increase the read capacity from 7.

If this were to be realized, it would be necessary to increase the size of the semiconductor chip, and an increase in costs would be unavoidable.

The present invention has been made in response to the above problems, and uses a semiconductor substrate in which a V-shaped groove is provided on one surface and has a barrier inside to generate a depletion layer in the vertical direction. It is an object of the present invention to provide a variable capacitance device configured to eliminate the conventional drawbacks without substantially increasing the area of the capacitance readout section by providing the capacitance readout section on the surface. Embodiments of the present invention will be described below with reference to the drawings. FIG. 3 is a sectional view showing a variable capacitance device according to an embodiment of the present invention, in which 10 is a P ⁺ layer, 11 is an N-type layer formed on this P ⁺ type layer 10, and 12 is an N-type layer 11.
13 is a V ^- shaped groove formed on the surface of the N-type layer 11, and 14 is a capacitive readout electrode (not shown) provided on the surface of this V-shaped groove 13. ). The specific structure of this capacitance readout section 14 is as shown in FIG.
A PN junction structure in which a capacitance readout electrode 16 is provided on the mold region 15, and a V-shaped groove 13 as shown in FIG.
An MIS structure in which a capacitive readout electrode 16 is provided on the surface via an insulating film 17, or a V
It is constituted by any of the shot key junction structures in which a metal 18 is provided on the surface of the character-shaped groove 13 and can also serve as a capacitive reading electrode and form a shot key barrier.

In the above configuration, a reverse bias voltage is applied between the depletion layer control electrode 6 and the common electrode 8 from a bias electrode (not shown). Here, this reverse bias voltage is a bias voltage in the direction of expanding the depletion layer from the barrier inside the semiconductor substrate toward the V-shaped groove, and in the example of ^FIG . The bias voltage is such that the voltage becomes a negative potential.
When this reverse bias voltage is small, as shown in Figure 7.
The depletion layer 9, which has started to spread from the PN junction 4 mainly toward the N-type layer 11 side with a low impurity concentration, does not spread much and is at a position where it does not reach the surface of the V-shaped groove 13.
Next, when the reverse bias voltage is increased, the depletion layer 9 expands greatly and advances to a position where it comes into contact with the surface of the V-shaped groove 13, as shown in FIG.

As a result, the capacitance change read out between the capacitance readout electrode 16 and the common electrode 8 becomes smaller as the reverse bias voltage increases, as the depletion layer expands, so that the capacitance change corresponding to the change in the reverse bias voltage is read out. become. That is, the change in capacitance between the capacitance read electrode 16 and the common electrode 8 is controlled by the reverse bias voltage applied between the depletion layer control electrode 6 and the common electrode 8 .

In this case, the effective area of the capacitive readout electrode 16 provided on the surface of the V-shaped groove 13 is as large as 1/sinθ times the area on the plane when the angle of V is θ°, so even if the chip size is the same, A larger capacitance change can be read out accordingly. In other words, when reading out the same capacitance change, a small chip size is sufficient.

The purpose of forming the V-shaped groove can be easily achieved by utilizing the well-known anisotropic etching.

FIG. 9 shows another embodiment of the present invention, in which V
A larger capacitance can be obtained by showing a structure in which a plurality of character-shaped grooves 13 are formed and by interconnecting each capacitance readout electrode 16 and common electrode 8, respectively.

In the embodiment, in order to form the depletion layer control electrode 6,
Although an example in which the P ⁺ type semiconductor layer 10 is formed is shown, these are not limited to semiconductor layers, but may include a barrier for generating a depletion layer in the vertical direction under application of a reverse bias voltage. For example, any structure can be selected from MIS structure, Schottky joint structure, etc. depending on the purpose.

As is clear from the above explanation, according to the present invention,
Since a semiconductor substrate having a V-shaped groove on one surface is used and a capacitance readout section is provided on the surface of this V-shaped groove, the area of the capacitance readout section on the plane can be substantially increased without increasing the area of the capacitance readout section. The capacity read from the capacity reading section can be increased.

Therefore, the size of the semiconductor chip can be reduced, resulting in cost reduction.

[Brief explanation of the drawing]

1 and 2 are sectional views showing a conventional example, and FIGS. 3 to 9 are sectional views showing an embodiment of the present invention. 4...PN junction, 6...depletion layer control electrode,
7, 16...capacitance readout electrode, 8...common electrode, 9
...Depletion layer, 13...V-shaped groove, 14...Capacitance reading section, 17...Insulating film, 18...Metal.

Claims (1)

[Claims] 1. (a) A semiconductor substrate having a V-shaped groove provided on one surface and having a barrier therein for generating a depletion layer in the vertical direction; (b) A semiconductor substrate provided in the V-shaped groove; (c) a depletion layer control section provided on the other surface of the semiconductor substrate; (d) a common electrode section provided on one surface of the semiconductor substrate; and (e) a capacitance readout section provided on the other surface of the semiconductor substrate; means for applying a reverse bias voltage between the depletion layer control section and the common electrode section so as to widen the depletion layer in the direction of the V-shaped groove; (f) the common electrode section and the capacitance readout section; 1. A variable capacitance device characterized in that it is configured to read a capacitance change between the capacitor and the capacitor. 2. The variable capacitance device according to claim 1, wherein the common electrode is arranged around the V-shaped groove. 3. The variable capacitance device according to claim 1, comprising a plurality of the V-shaped grooves. 4. The variable capacitance device according to any one of claims 1 to 3, wherein the capacitance reading section has any one of a PN junction structure, an MIS structure, and a Schottky junction structure. 5. The variable capacitance device according to claim 1, wherein the depletion layer control section has one of a PN junction structure, an MIS structure, and a Schottky junction structure.