JPS6328348B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a variable capacitance device having three terminals, which is designed to reduce the chip size.

The structure shown in Fig. 1 is an example of a three-terminal variable capacitance device configured to separately provide a depletion layer control electrode for controlling the extension of the depletion layer and a capacitance readout electrode for reading the capacitance change due to the depletion layer. It has been known. In the same figure, 1 is the N ⁺ type layer, and 2 is this layer.
N type layer formed on N ⁺ type layer 1, 3 is N type layer 2
4 is a ^PN junction, 5 is an insulating film, 6 is a depletion layer control electrode provided on the P ⁺ type layer 3, and 7 is provided on the insulating film 5. A capacitance readout electrode 8 is a common electrode for both electrodes 6 and 7 provided on the N ⁺ type layer 1. In the above, when a reverse bias voltage is applied between the depletion layer control electrode 6 and the common electrode 8, the PN junction 4
Since the depletion layer 9 mainly expands toward the N-type layer 2 side where the impurity concentration is low, the capacitance readout electrode 7 and the common electrode 8
A change in capacitance occurs between the capacitance and the capacitance readout electrode 7, and a capacitance change corresponding to a change in reverse bias voltage is read out from the capacitance reading electrode 7. Compared to the conventional two-terminal variable capacitance device configured to serve as both the depletion layer control electrode and the capacitance readout electrode, such a three-terminal variable capacitance device can achieve a steep capacitance change in response to a change in reverse bias voltage. It has the advantage of being

However, as mentioned above, the impurity concentration of the N-type layer 2 for expanding the depletion layer 9 is usually 10 ¹⁴ /cm ³
However, in order to obtain the desired capacitance change with this value, it is necessary to set the spacing between the P ⁺ type layers 3 to several micrometers, so the common electrode 8
If it is desired to increase the capacitance read out between the capacitance readout electrode 7 and the capacitance readout electrode 7, a large number of the P ⁺ type layers 3 must be provided as shown in FIG. This P ⁺ type layer 3
Since the width of the depletion layer control section including the depletion layer control electrode 6 is required to be a value of 10 to 20 microns, most of the area of the semiconductor chip is occupied by the depletion layer control section including the depletion layer control electrode 6. It becomes difficult to increase the read capacity from 7.

If this were to be realized, it would be necessary to increase the size of the semiconductor chip, and an increase in costs would be unavoidable.

The present invention has been made in response to the above problems, and uses a semiconductor substrate in which a V-shaped groove is provided on one surface and has a barrier inside to generate a depletion layer in the vertical direction. It is an object of the present invention to provide a variable capacitance device configured to eliminate the conventional drawbacks without substantially increasing the area of the capacitance readout section by providing the capacitance readout section on the surface. Embodiments of the present invention will be described below with reference to the drawings. FIG. 3 is a cross-sectional view showing a variable capacitance device according to an embodiment of the present invention, where 10 is a P ⁺ type layer and 11 is a P + type layer.
An N type layer formed on the P ⁺ type layer 10, 12 an N ⁺ type region selectively formed in the N type layer 11, 13
1 is a V-shaped groove formed on the surface of the N-type layer 11;
4 is N ⁺ selectively formed within the V-shaped groove 13 surface.
15 is a capacitive reading electrode formed of, for example, an ohmic electrode provided in the N ⁺ type region 14, and 16 is an electrode for applying a reverse bias voltage provided in the N ⁺ type region 12.

In the above configuration, a reverse bias voltage is applied between the depletion layer control electrode 6 and the electrode 16. Here, this reverse bias voltage is a bias voltage in a direction that expands the depletion layer from the barrier inside the semiconductor substrate toward the V-shaped groove.For example, in the example shown in FIG. 4, if the N-type layer 11 is set to the reference potential, ^P The bias voltage is such that the mold layer 10 has a negative potential. When this reverse bias voltage is small, as shown in FIG. 4, the depletion layer 9 that has started to spread from the PN junction 4 mainly toward the N-type layer 11 side with a low impurity concentration does not spread much, and the V-shaped groove 13
It is in a position that does not reach the surface. Next, when the reverse bias voltage is increased, the depletion layer 9 expands greatly and advances to a position where it comes into contact with the surface of the V-shaped groove 13, as shown in FIG.

As a result, the capacitance change between the capacitance readout electrode 15 and the depletion layer control electrode 6 becomes smaller as the reverse bias voltage increases, as the depletion layer expands.
From between 5 and 6, capacitance changes corresponding to changes in reverse bias voltage are read out. That is, the change in capacitance between the capacitance read electrode 15 and the depletion layer control electrode 6 is controlled by the reverse bias voltage applied between the depletion layer control electrode 6 and the electrode 16.

In this case, the effective area of the capacitive readout electrode 15 provided on the surface of the V-shaped groove 13 is 1/sinθ times the area on the plane when the angle of V is θ, so even if the chip size is the same, It is possible to read a capacitance change larger than 1 minute. In other words, when reading out the same capacitance change, a small chip size is sufficient.

The purpose of forming the V-shaped groove can be easily achieved by utilizing the well-known anisotropic etching.

FIG. 6 shows another embodiment of the present invention, in which V
A larger capacitance can be obtained by showing a structure in which a plurality of character-shaped grooves 13 are formed and by interconnecting the respective capacitance readout electrodes 15.

In the embodiment, an example was shown in which the P ⁺ type semiconductor layer 10 was formed to form the depletion layer control electrode 15.
These layers are not limited to semiconductor layers, but may be any layer that has a barrier for generating a depletion layer in the vertical direction under the application of a reverse bias voltage, for example, in an MIS structure, a Schottky junction structure, etc. You can select any one depending on your purpose. Further, the capacitive readout electrode 15 is not limited to an ohmic electrode, but may be formed of any of them.

As is clear from the above explanation, according to the present invention,
Since a semiconductor substrate having a V-shaped groove on one surface is used and a capacitance readout section is provided on the surface of this V-shaped groove, the area of the capacitance readout section on the plane can be substantially increased without increasing the area of the capacitance readout section. The capacity read from the capacity reading section can be increased.

Therefore, the size of the semiconductor chip can be reduced, resulting in cost reduction.

[Brief explanation of drawings]

1 and 2 are sectional views showing a conventional example, and FIGS. 3 to 6 are sectional views showing an embodiment of the present invention. 4...PN junction, 6... Depletion layer control electrode, 9
...depletion layer, 13...V-shaped groove, 15...capacitance readout electrode.

Claims (1)

[Scope of Claims] 1 (a) a semiconductor substrate having a V-shaped groove provided on one surface and having a barrier therein for generating a depletion layer in the vertical direction; (b) a semiconductor substrate provided in the V-shaped groove; (c) a depletion layer control section provided on the other surface of the semiconductor substrate; (d) a bias voltage application electrode provided on one surface of the semiconductor substrate; (e) the above (f) means for applying a reverse bias voltage between the depletion layer control section and the bias application electrode so as to spread the depletion layer from the barrier toward the V-shaped groove; (f) the depletion layer control section; and the capacitance reading section, the variable capacitance device being configured to read a capacitance change between the capacitor and the capacitance reading section. 2. The variable capacitance device according to claim 1, wherein the bias applying electrode is arranged around the V-shaped groove. 3. The variable capacitance device according to claim 1, comprising a plurality of the V-shaped grooves. 4 The capacitance readout section has an ohmic electrode structure, P-
4. The variable capacitance device according to claim 1, wherein the variable capacitance device has any one of an N junction structure, an MIS structure, and a Schottky junction structure. 5. The variable capacitance device according to claim 1, wherein the depletion layer control section has one of a PN junction structure, an MIS structure, and a Schottky junction structure.