JPS6328498B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a variable capacitance device configured such that its capacitance changes rapidly in response to changes in reverse bias voltage.

Conventionally, a PN junction element as shown in FIG. 1 has been used as a variable capacitance device. In the figure, 1 is an N-type semiconductor layer, 2 is a P-type semiconductor region,
3 is a PN junction; 4 and 5 are electrodes provided in the N-type layer 1 and P-type region 2, respectively; 6 and 7
are lead terminals provided on the electrodes 4 and 5, respectively, and 8 is a depletion layer extending from the PN junction 3 toward the N-type layer 1, which has a low impurity concentration. In the above, the depletion layer 8 expands and contracts in response to the reverse bias voltage applied between the lead terminals 6 and 7, and the capacitance change based on this is read out between the lead terminals 6 and 7.

However, the conventional variable capacitance device using the above-mentioned PN junction element has the following drawbacks.

(1) In order to utilize the bias voltage dependence of the depletion layer capacitance in the PN junction, the minimum capacitance value is determined by the impurity concentration of the semiconductor region, while the maximum capacitance value is determined by the increase in the conductance component. For this reason, it is practically impossible to increase the range of capacitance change in a state where Q is large, and since the change in Q becomes large as the capacitance changes, it is difficult to design the circuit.

(2) Since the bias voltage applied to change the capacitance and the readout of the capacitance change are performed through a common lead-out terminal, unnecessary capacitance changes are likely to occur due to the input signal voltage itself when applied to a resonant circuit, etc. resulting in signal deterioration. Also, a special circuit configuration is required to reduce the interaction between the input signal voltage and bias voltage.
Its uses are limited.

(3) The impurity concentration in the semiconductor region, which determines the depletion layer capacitance, is controlled by a diffusion method or ion implantation method, but since the yield is generally low, it is not practical to integrate it into an IC circuit. It's impossible.

The present invention has been made in response to the above problems, and includes a second conductive type semiconductor region selectively formed on one surface of the first conductive type semiconductor layer and a second conductive type semiconductor region formed on the other surface of the first conductive type semiconductor layer. Using semiconductor substrates each having a barrier for generating a depletion layer,
It is an object of the present invention to provide a variable capacitance device configured to eliminate the conventional drawbacks by operating the second conductivity type semiconductor region as a depletion layer limiting region and as a capacitance readout section.

Embodiments of the present invention will be described below with reference to the drawings.
FIG. 2 is a cross-sectional view showing a variable capacitance device according to an embodiment of the present invention, in which 9 is a second conductive type semiconductor layer, for example, an N-type layer, and 10 is a first conductive type semiconductor layer formed on this N-type layer 9. , for example, a P-type layer; 11 is a second conductivity type semiconductor region selectively formed in the P-type layer 10, for example, an N-type region; 12 is an insulating film; 13 is a depletion layer provided in the N-type layer 9; A control electrode 14 is a capacitive readout electrode provided in the N-type region 11, and 15 is a common electrode for the electrodes 13 and 14.

In the above configuration, a reverse bias voltage V _R is applied between the depletion layer control electrode 13 and the common electrode 15, that is, the P-type layer is connected to the N-type layer so that the depletion layer 8 is expanded from the PN junction toward the P-type layer. When a bias voltage for biasing to the negative side is applied, a depletion layer 8 is formed from the PN junction 3 mainly to the P-type layer 10 side with a low impurity concentration.
begins to expand, and the width d of this depletion layer 8 changes depending on the reverse bias voltage _VR , as shown by the solid line in Figure 3A.
It spreads in proportion to the increase in _VR . In addition, as shown in FIG.
When depletion layer 8 expands as a result of an increase in reverse bias voltage V _R and reaches this N-type region 11, the expansion toward this region 11 is prevented. That is, in this case, the N type region 11 operates as a depletion layer limiting region. Therefore, the subsequent expansion of the depletion layer 8 will proceed intensively toward the upper part of the P-type layer 10 adjacent to the N-type region 11. When a depletion layer limiting region exists in this way, the width d of the depletion layer 8 with respect to the reverse bias voltage V _R changes as shown by the dotted line in FIG. It increases rapidly as the bias voltage V _R increases. This means that the capacitance can be varied over a wide range for the same change in reverse bias voltage _VR . FIG. 3B shows the change characteristics of the capacitance C with respect to the reverse bias voltage V _R , and the two characteristics correspond to FIG. 3A, respectively.

As a result, the capacitance between the capacitance readout electrode 14 and the common electrode 15 becomes the junction capacitance at the boundary between the portion of the P-type region 10 where the depletion layer 8 has not expanded and the N-type region 11, and this junction capacitance is the depletion capacitance. The reverse bias voltage changes in response to changes in layer 8.
As V _R increases, the depletion layer 8 expands, so it changes in the direction of becoming smaller.

That is, from between the capacitance reading electrode 14 and the common electrode 15, a capacitance change controlled by the reverse bias voltage _VR applied between the depletion layer control electrode 13 and the common electrode 15 is read out.

FIG. 4 shows another embodiment of the present invention, and particularly shows an example in which the cross-sectional shape of the N-type region 11 is modified. That is, a case is shown in which the N-type region 11 is formed with a double structure of a first N-type region 11A with a small radius of curvature and a second N-type region 11B with a large radius of curvature. By varying the radius of curvature around the cross-sectional shape of the N-type region 11 in this way, it is possible to change the state of expansion of the depletion layer in response to changes in reverse bias voltage, and in particular to reduce capacitance changes when the reverse bias voltage is small. It can be made gentle. As a result, the area contributing to an increase in capacitance readout can be increased, and the area of the semiconductor chip can be reduced when reading out the same capacitance change.

The double structure described above can be easily formed by using the well-known selective diffusion method.
Moreover, it is not limited to a double structure, but can also be a multiplex structure.

FIG. 5 shows another embodiment of the present invention, in which a second P-type layer 16 (so-called
This shows an example in which a P ^- type high resistivity layer is provided.
By providing the high specific resistance layer 16 of the same conductivity type adjacent to the P-type layer 10 in this way, the spread of the depletion layer when the reverse bias voltage that does not contribute to capacitance changes is small can be increased, so that the reverse bias voltage can be increased. Loss can be reduced. In addition to this, the parasitic capacitance at that time can also be suppressed to a small level.

FIG. 6 shows another embodiment of the present invention, and shows another modification of the cross-sectional shape of the N-type region 11.

In each of the above embodiments, the barrier for generating a depletion layer by providing a depletion layer control electrode is as follows:
Although an example is shown in which a PN junction structure is used, the present invention is not limited to this, and other structures such as an MIS structure or a Schottky junction structure may be used.

As is clear from the above explanation, according to the present invention,
A semiconductor substrate each having a second conductivity type semiconductor region selectively formed on one surface of the first conductivity type semiconductor layer and a barrier for generating a depletion layer formed on the other surface of the first conductivity type semiconductor layer. Since the second conductivity type semiconductor region is configured to operate as a depletion layer limiting region and as a capacitance readout section, a wider capacitance change can be achieved than in the case of simply using the depletion layer capacitance due to a reverse bias voltage. can be made to do so. Furthermore, since the depletion layer control section and the capacitance readout section have independent structures, it is possible to avoid adverse effects caused by input signals. Furthermore, since it is not necessary to determine the depletion layer capacitance only based on the impurity concentration of the semiconductor region, there is no need for complicated means to accurately control the impurity concentration, so integration can be achieved without reducing yield.

Note that the conductivity type can be arbitrarily switched between P type and N type.

[Brief explanation of the drawing]

Figure 1 is a sectional view showing a conventional example, Figures 2 and 4.
5 and 6 are all cross-sectional views showing embodiments of the present invention, and FIG. 3 is a graph for explaining the present invention. 3...PN junction, 8... Depletion layer, 11, 11
A, 11B...Depletion layer limiting region, 12...Insulating film, 13...Depletion layer control electrode, 14...Capacitance reading electrode, 15...Common electrode.

Claims (1)

[Claims] 1. A first conductivity type semiconductor layer, a second conductivity type region provided on one side of the first conductivity type semiconductor layer, and a junction for generating a depletion layer. a second conductivity type semiconductor layer provided on the other surface of the first conductivity type semiconductor layer in order to perform the above operations; a capacitive readout electrode provided on the second conductivity type region; and the first conductivity type semiconductor layer. a common electrode disposed near the second conductivity type region on one surface of the second conductivity type semiconductor layer; a depletion layer control electrode, and a bias voltage source connected between the common electrode and the depletion layer control electrode for biasing the depletion layer so as to spread from the junction toward the first conductivity type semiconductor layer. A variable capacitance device comprising: a variable capacitance device configured to read a capacitance between the common electrode and a capacitance readout electrode. 2. The variable capacitance device according to claim 1, wherein the second conductive type semiconductor region has a substantially hemispherical shape. 3. The variable capacitance device according to claim 1, wherein the second conductive type semiconductor region has a hemispherical cross-sectional shape with different radii of curvature. 4. The variable capacitor device according to claim 3, wherein the impurity concentration of a portion of the first conductive type semiconductor layer near the second conductive type semiconductor layer is lower than that of the other portion.