JPS586182A - Variable capacitor - Google Patents
Variable capacitorInfo
- Publication number
- JPS586182A JPS586182A JP10426881A JP10426881A JPS586182A JP S586182 A JPS586182 A JP S586182A JP 10426881 A JP10426881 A JP 10426881A JP 10426881 A JP10426881 A JP 10426881A JP S586182 A JPS586182 A JP S586182A
- Authority
- JP
- Japan
- Prior art keywords
- depletion layer
- capacitance
- electrode
- capacity
- read
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 title abstract description 4
- 239000004065 semiconductor Substances 0.000 claims abstract description 11
- 230000004888 barrier function Effects 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 239000012535 impurity Substances 0.000 abstract description 7
- 238000000034 method Methods 0.000 abstract description 2
- 230000008859 change Effects 0.000 description 12
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000004044 response Effects 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/92—Capacitors having potential barriers
- H01L29/93—Variable capacitance diodes, e.g. varactors
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、半導体チップの側面に容量続出部を設けるよ
うに構成した三端子を有する可変容量装置に関するもの
である。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a variable capacitance device having three terminals configured to provide a capacitance extension portion on the side surface of a semiconductor chip.
可変容量装置として従来第１図のようなＰＮ接合素子を
利用することが行われている。同図において、ｌはＮ型
半導体層、２はＰ型半導体領域、３はＰＮ接合部、４お
よび５は上記Ｎ型層１およびＰ型頭域２に各々設けられ
た電極、６および７は上記電極４および５に各々設けら
れた引出し端子、８はＰＮ接合部３から主として不純物
濃度の低いＮ型層ｌ側に拡がる空乏層である。以上にお
いて、引出し端子６および７間に加えられる逆バイアス
電圧に応じて空乏層８が伸縮し、これに基づ（容量変化
が引出し端子６および７間で読み出されるようになって
ｈる。Conventionally, a PN junction element as shown in FIG. 1 has been used as a variable capacitance device. In the figure, l is an N-type semiconductor layer, 2 is a P-type semiconductor region, 3 is a PN junction, 4 and 5 are electrodes provided in the N-type layer 1 and P-type head region 2, respectively, and 6 and 7 are Output terminals 8 provided on the electrodes 4 and 5 are depletion layers extending from the PN junction 3 mainly toward the N-type layer l side having a low impurity concentration. In the above, the depletion layer 8 expands and contracts in response to the reverse bias voltage applied between the lead terminals 6 and 7, and based on this (capacitance change is read out between the lead terminals 6 and 7).
しかしながら以上のようなＰＮ接合素子を利用した従来
の可変容量装置は以下のような欠点な有している。However, the conventional variable capacitance device using the above-mentioned PN junction element has the following drawbacks.
（ＩＩＰＮ接合における空乏層容量のバイアス電圧依存
性を利用するため、最小容量値は半導体領域の不純物濃
度により決定され、一方最大容量値はコンダクタンス成
分の増大により決定される。(In order to utilize the bias voltage dependence of the depletion layer capacitance at the IIPN junction, the minimum capacitance value is determined by the impurity concentration of the semiconductor region, while the maximum capacitance value is determined by the increase in the conductance component.
このためＱが大きい状態で容量変化中を太き（と−るこ
とば実用上不可能となり、また容量変化に伴５Ｑの変化
が大きくなるので回路設計上困難を伴なう。For this reason, it is practically impossible to make the change in capacitance thick when Q is large, and the change in 5Q becomes large as the capacitance changes, making it difficult to design the circuit.
（２）容量を変化させるためのバイアス電圧印加および
容量変化の読み出しを共通の引出し端子で行っているた
め、共振回路等に応用した時に入力信号電圧自体によっ
て不必要な容量変化を起こし易（なり信号劣化をもたら
す。また入力信号電圧とバイアス電圧との相互作用が少
なくなるような特別な回路構成が必要とされるので、用
途が限定されてしまう。(2) Since the bias voltage applied to change the capacitance and the readout of the capacitance change are performed using a common lead terminal, it is easy to cause unnecessary capacitance changes due to the input signal voltage itself when applied to a resonant circuit, etc. This results in signal deterioration, and requires a special circuit configuration that reduces the interaction between the input signal voltage and the bias voltage, which limits its applications.
（３）空乏層容量を決定するための半導体領域の不純物
濃度が拡散法あるいはイオンインプランテーション法等
の制御手段により行われるが、一般に歩留りが悪いので
ＩＣ回路へ集積化することは実用上不可能である。(3) The impurity concentration in the semiconductor region to determine the depletion layer capacitance is controlled by a diffusion method or ion implantation method, but the yield is generally low and it is practically impossible to integrate it into an IC circuit. It is.
本発明は以上の問題に対処してなされたもので、一つの
表面に空乏層を発生させるための障壁を有する半導体基
板を用いこの基板の側面に容量続出部を設けることによ
り、実質的に容量続出部の平面的な面積を増加させるこ
となく容量変化を増加させるようにして従来欠点を除去
し得るように構成した可変容量装置を提供するものであ
る。The present invention has been made in response to the above-mentioned problems, and uses a semiconductor substrate having a barrier for generating a depletion layer on one surface, and provides a capacitance continuous portion on the side surface of this substrate, thereby substantially increasing the capacitance. The present invention provides a variable capacitance device configured to increase capacitance change without increasing the planar area of a continuous portion, thereby eliminating the conventional drawbacks.
以下第２図を参照して本発明実施例による可変容量装置
を説明する。同図にケいて、９はＮ１型層、１０はこの
Ｎ型層９上に形成されたＰ型層、１１は側面部でＰＮ接
合部３との間に傾斜角θを有している。１２は上記Ｎ型
層９に設けられた空乏層制御電極、１３は上記側面部ｌ
】に設けられた例えばオーミック電極から成る容量続出
電極、１４はオーミック電極、１５は絶縁膜である。A variable capacitance device according to an embodiment of the present invention will be described below with reference to FIG. In the figure, 9 is an N1 type layer, 10 is a P type layer formed on this N type layer 9, and 11 is a side surface having an inclination angle θ between it and the PN junction 3. 12 is a depletion layer control electrode provided on the N-type layer 9, and 13 is the side surface l.
14 is an ohmic electrode, and 15 is an insulating film.
以上の構成において、空乏層制御電極１２と電極１４と
の間に逆バイアス電圧ＶＲを印加すると、逆バイアス電
圧の増加につれて空乏層８がＰＮ接合３から主として不
純物濃度の低いＰ型層１０側に拡がり始めその巾ｄが増
加する。同時に側面部１１のスロープ（＃４斜面）Ａ下
の空乏層８の寸法りも増加し、一方スロープＡ下の空乏
層８が存在していない部分の寸法Ｂは徐々に減少してい
（。In the above configuration, when a reverse bias voltage VR is applied between the depletion layer control electrode 12 and the electrode 14, as the reverse bias voltage increases, the depletion layer 8 moves mainly from the PN junction 3 to the P-type layer 10 side with a low impurity concentration. It begins to expand and its width d increases. At the same time, the size of the depletion layer 8 under the slope (#4 slope) A of the side surface portion 11 also increases, while the size B of the portion where the depletion layer 8 does not exist under the slope A gradually decreases (.
これにより容量読出電極１３と空乏層制御電極１２との
間に空乏層８を介したコンデンサが形成されて容量変化
が生じ、空乏層中ｄおよび寸法りが拡がる程上記電極１
３および１２間で読み出される容量変化は小さくなり、
逆バイアス電圧の変化に対応した容量変化が読み出され
るようになる。すなわち空乏層制御電極１２と電極１４
との間に印加される逆バイアス電圧によって、容量読出
電極１３と空乏層制御電極１２との間で読み出される容
量変化は制御されることになる。この容量読出電極１３
で読み出される容量は、上記空乏層８による容量の他に
絶縁膜１５による容量も含まれる。As a result, a capacitor is formed between the capacitance readout electrode 13 and the depletion layer control electrode 12 via the depletion layer 8, and a capacitance change occurs.
The capacitance change read between 3 and 12 becomes smaller,
Capacitance changes corresponding to changes in reverse bias voltage are read out. That is, the depletion layer control electrode 12 and the electrode 14
The change in capacitance read between the capacitance read electrode 13 and the depletion layer control electrode 12 is controlled by the reverse bias voltage applied between the capacitance read electrode 13 and the depletion layer control electrode 12. This capacitance readout electrode 13
The capacitance read out includes not only the capacitance due to the depletion layer 8 but also the capacitance due to the insulating film 15.
上記側面部１］に設けられた容量読出電極１３の有」
効面積はその角度ｒとした時、平面上の面積の”／ｓｉ
ｎθ倍と太き（することができる。したかつて平面的に
同−寸、法のチップサイズとした場合でも、より大きな
容量変化を読み出すことができ、同じ容量変化を読み出
す場合は小さなチップサイズで事足りることができる。The effective area of the capacitive readout electrode 13 provided on the side surface 1 is equal to the area on the plane "/si" when its angle is r.
It is possible to read out a larger change in capacitance even if the chip size is the same size and the same size on a plane. I can have enough.
角度θ−−小さくなる程容量変化の倍率を太き（するこ
とができるが、このθの値は目的に応じて任意に選択す
ることができる。The smaller the angle θ, the larger the magnification of capacitance change (the value of θ can be arbitrarily selected depending on the purpose).
側面部１］の角度θを形成する手段は周知の異方性エツ
チングを利用することによって容易に目的を達成するこ
とができる。The purpose of forming the angle θ of the side surface portion 1 can be easily achieved by using well-known anisotropic etching.
空乏層制御電極１２を設けて空乏層８を発生させるため
の障壁としては、実施例ではＰ型層ｌＯとＮ型層９との
ＰＮ接合構造を利用する場合について説明したが、何ら
これに限定されることなく例えばＭＩＳ構造、ショット
キー接合構造等を選択しても良い。また容量読出電極１
３もオーミック電極に限らずそれらのいずれかで構成し
ても良い８以上のようにして得られる王、端子の可変容
量装置は、例えばＡＭラジオフロントエンド部の電子同
調回路をＩＣ化する際に同時に組み込むことができ、上
記ＩＣ製造プロセスをそのまま利用して形成することが
可能となる。この点従来の可変容量装置では、ＩＣ製造
プロセスをそのまま利用してＩＣ化することが困難であ
ったため、外付は部品として別個に同調回路に接続する
必要があった。As a barrier for generating the depletion layer 8 by providing the depletion layer control electrode 12, in the embodiment, a case has been described in which a PN junction structure between a P-type layer IO and an N-type layer 9 is used, but this is not limited to this. For example, an MIS structure, a Schottky junction structure, etc. may be selected. Also, capacitance readout electrode 1
3 may also be composed of any of these, not limited to ohmic electrodes. The terminal variable capacitance device obtained as described above is useful when, for example, converting an electronic tuning circuit of an AM radio front end into an IC. They can be incorporated at the same time, and can be formed using the above IC manufacturing process as is. In this respect, with conventional variable capacitance devices, it was difficult to use the IC manufacturing process as is to convert them into an IC, so the external components had to be connected to the tuning circuit separately as components.
以上説明して明らかなように本発明によれば、一つの表
面に空乏層を発生させるための障壁を有する半導体基板
を用いこの基板の側面に容量続出部を設けることにより
、実質的に容量読出部の平面的な面積を増加させること
なく容量変化を増加させるように構成するものであるか
ら、単に逆バイアス電圧による平面的な空乏層容量を利
用する場合に比べ容易に容量を増加させることができる
。As is clear from the above description, according to the present invention, a semiconductor substrate having a barrier for generating a depletion layer on one surface is used, and a capacitance continuous portion is provided on the side surface of this substrate, so that capacitance reading can be substantially performed. Since the structure is configured to increase the capacitance change without increasing the planar area of the part, it is easier to increase the capacitance than when simply using the planar depletion layer capacitance by reverse bias voltage. can.
また空乏層制御部と容量続出部とが独立した三端子構造
となっているために、入力信号による悪影響を避けるこ
とができる。さらに、半導体領域の不純物濃度だけで空
乏層容量を決定する必要はないので、不純物濃度を正確
に制御するための複雑な手段は不要となるため、歩留り
低下なしに集積化が可能となる。Furthermore, since the depletion layer control section and the capacitance extension section have an independent three-terminal structure, it is possible to avoid adverse effects caused by input signals. Furthermore, since it is not necessary to determine the depletion layer capacitance only by the impurity concentration of the semiconductor region, there is no need for complicated means to accurately control the impurity concentration, so integration can be achieved without reducing yield.
第１図および第２図は従来および本発明実施例を示す断
面図である。
３・・・ＰＮ接合部、８・・・空乏層、１１・・・側面
部、１２・・・空乏層制御電極、１３・・・容量読出電
極、１５・・・絶縁膜。
特許出願人 クラリオフ株式会社FIGS. 1 and 2 are cross-sectional views showing a conventional device and an embodiment of the present invention. 3... PN junction, 8... Depletion layer, 11... Side surface portion, 12... Depletion layer control electrode, 13... Capacitance read electrode, 15... Insulating film. Patent applicant Clarioff Co., Ltd.
Claims (1)
表面および側面とを有する半導体基板の。 上記油表面に空乏層制御部を側面に容量続出部を各々設
け、上記空乏層制御部を逆バイアスすることにより上記
障壁がら空乏層を上記側面に到達させ、これにより上記
容量読出部と空乏層制御部間で容量変化を読み出すよう
に構成したことを特徴とする可変容量装置。 ２、上記側面が傾斜面であることを特徴とする特許請求
の範囲第１項記載の可変容量装置。 ３、上記容量読出部がオーミック電極構造、Ｐ−Ｎ接合
構造、ＭＩ８構造、ショットキー接合構造のいずれかで
あることを特徴とする特許請求の範囲第１項又は第２項
記載の可変容量装置。 ４、上記空乏層制御部がＰ−Ｎ接合構造、ＭＩＳ構造、
ショットキー接合構造のいずれかであることを特徴とす
る特許請求の範囲第１項乃至第３項のいずれかに記載の
可変容量装置。Claims: 1. - A semiconductor substrate having an oil surface and side surfaces with a surface and a barrier for generating a depletion layer. A depletion layer control section is provided on the oil surface, and a capacitance extension section is provided on the side surface, and by reverse biasing the depletion layer control section, the depletion layer is caused to reach the side surface through the barrier, thereby causing the capacitance readout section and the depletion layer to reach the side surface. A variable capacitance device characterized in that it is configured to read capacitance changes between control sections. 2. The variable capacitance device according to claim 1, wherein the side surface is an inclined surface. 3. The variable capacitance device according to claim 1 or 2, wherein the capacitance readout section has any one of an ohmic electrode structure, a PN junction structure, an MI8 structure, and a Schottky junction structure. . 4. The depletion layer control section has a PN junction structure, an MIS structure,
The variable capacitance device according to any one of claims 1 to 3, characterized in that it has any one of Schottky junction structures.
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10426881A JPS586182A (en) | 1981-07-03 | 1981-07-03 | Variable capacitor |
| GB08219002A GB2103012A (en) | 1981-07-03 | 1982-07-01 | Variable capacitor |
| FR8211672A FR2509093A1 (en) | 1981-07-03 | 1982-07-02 | VARIABLE CAPACITOR |
| DE19823224835 DE3224835A1 (en) | 1981-07-03 | 1982-07-02 | VARIABLE CAPACITOR |
| NL8202682A NL8202682A (en) | 1981-07-03 | 1982-07-02 | VARIABLE CAPACITANCE. |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10426881A JPS586182A (en) | 1981-07-03 | 1981-07-03 | Variable capacitor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS586182A true JPS586182A (en) | 1983-01-13 |
Family
ID=14376172
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10426881A Pending JPS586182A (en) | 1981-07-03 | 1981-07-03 | Variable capacitor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS586182A (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56104266A (en) * | 1980-01-25 | 1981-08-19 | Yokogawa Hokushin Electric Corp | Ultrasonic measuring apparatus |
-
1981
- 1981-07-03 JP JP10426881A patent/JPS586182A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56104266A (en) * | 1980-01-25 | 1981-08-19 | Yokogawa Hokushin Electric Corp | Ultrasonic measuring apparatus |
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