JPS5843579A - Variable capacity element - Google Patents
Variable capacity elementInfo
- Publication number
- JPS5843579A JPS5843579A JP14096781A JP14096781A JPS5843579A JP S5843579 A JPS5843579 A JP S5843579A JP 14096781 A JP14096781 A JP 14096781A JP 14096781 A JP14096781 A JP 14096781A JP S5843579 A JPS5843579 A JP S5843579A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- terminal
- capacity
- semiconductor layer
- depletion layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims abstract description 21
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 239000012212 insulator Substances 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/92—Capacitors having potential barriers
- H01L29/93—Variable capacitance diodes, e.g. varactors
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、空乏層制御用バイアス端子と容量続出用端子
とが直流的に独立するように構成された可変容量素子に
関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a variable capacitance element configured such that a bias terminal for controlling a depletion layer and a terminal for extending a capacitance are independent in terms of direct current.
従来における可変容量素子として第1図のようなPN接
合ダイオードを利用することが行われている。A PN junction diode as shown in FIG. 1 has been conventionally used as a variable capacitance element.
同図におい′C1はN型半導体層;2はこのN型層lに
接してPN接合部3を形成するP型層、4.5は上記N
型層lおよびP型層2に各々設けられたオーミック電極
、6は、1−ミック電極4.5間に逆方向バイアスとな
るように接続された空乏層制御用・(イアスミ圧、7は
容量続出用端子部である。In the figure, 'C1 is an N-type semiconductor layer; 2 is a P-type layer that is in contact with this N-type layer l and forms a PN junction 3; 4.5 is the above-mentioned N-type semiconductor layer;
Ohmic electrodes provided on the type layer 1 and the P-type layer 2, 6 are for depletion layer control connected between 1 and mic electrodes 4.5 to provide a reverse bias (Iasmium pressure, 7 is the capacitance) This is the terminal part for continuous output.
以上の構成にお’t、−aて、上記空乏層制御用・;イ
アスミ圧6′を可変するごとによりPN接合部3両側に
(主として゛不純物濃度の低い側に)拡がる空乏層8の
巾りが変化するので、これに基づく容量値の変化が容量
続出用端子部7から読み出されるようになっている。In the above configuration, the depletion layer 8 spreads on both sides of the PN junction 3 (mainly toward the side with lower impurity concentration) by varying the depletion layer control insulator pressure 6'. Since the width changes, the change in capacitance value based on this change is read out from the capacitance successive output terminal section 7.
しかしながら以上のような従来の可変容量素子は、2端
子素子であるために空乏層制御用バイアス端子と容量続
出用端子とが共通電極によって構成されて直流的に独立
していないので、同調回路等に適用した場合に入力信号
によって不必要な容量変化等が引き起こされて同調ずれ
等の原因となる場合がある。However, since the conventional variable capacitance element described above is a two-terminal element, the bias terminal for controlling the depletion layer and the terminal for increasing the capacitance are constituted by a common electrode and are not independent in terms of direct current. When applied to a device, the input signal may cause unnecessary capacitance changes, etc., which may cause tuning errors.
したがって用途が制約されてしまう欠点があった。Therefore, there was a drawback that the applications were restricted.
本発明は以上の欠点を除去するためなされたもので・P
N!合部合部酸形成る一方何0半導体層に第1電極およ
び絶縁膜を介して第2電極を各々設け、上記第1電極齋
空乏層制御用六イアス端子としてかつ第2電極5を容量
続出用端子として用いることにより、上記両端子を直流
的に独立させるように構成した可変容量素子を提供する
ものである。以下図面を参照して本i、!A実施例を説
明する。第;図は本発明実施例による可変容量素子を示
す断面図で第1図と同一部分は同一番号で示し、9はP
型半導体層2に設けられたオーミック電極、10はこの
P型半導体層2に絶縁膜1】例えばシリコン酸化膜を介
して設けられた電極、12ぽ容量続出用端子部である。The present invention has been made to eliminate the above-mentioned drawbacks.
N! While forming a joint joint, a first electrode and a second electrode are provided on each of the semiconductor layers via an insulating film, and the first electrode serves as a depletion layer control terminal and the second electrode 5 serves as a capacitor. The present invention provides a variable capacitance element configured so that the two terminals are independent in terms of direct current by being used as a terminal for the purpose of the present invention. Book i, with reference to the drawings below! Example A will be explained. Figure 1 is a cross-sectional view showing a variable capacitance element according to an embodiment of the present invention, and the same parts as in Figure 1 are designated by the same numbers, and 9 is a P
The ohmic electrode 10 provided on the P-type semiconductor layer 2 is an electrode provided on the P-type semiconductor layer 2 via an insulating film 1, for example, a silicon oxide film, and is a terminal portion for continuous output of a 12-porous capacitance.
以上の構成におい七、上記空乏層制御用バイアス電圧6
を可変することによりPN接各部の両側に拡がる空乏層
8の巾りは変化するようになる。これKよ−て容量読出
用端子部”′かff、:、9.、:、口上記空乏層°の
巾りの変化に応じた容量値の変化 読み出される。この
場合上記電極10、絶縁膜11およびN型半導体層2は
いわゆるMO8構造を構成しているので、上記容量読出
用端子12からは上記空乏層8の変化分による4容量に
、上記絶縁膜1】自身による容量およびP型半導体層1
.とN型半導体層2による容量が直列に加えられター直
列容量が読人出されることになる。In the above structure, 7. The bias voltage for controlling the depletion layer 6
By varying this, the width of the depletion layer 8 extending on both sides of each PN contact portion can be varied. From this, a change in capacitance value is read out according to a change in the width of the depletion layer above the capacitance reading terminal section ``'' or ff. 11 and the N-type semiconductor layer 2 constitute a so-called MO8 structure, so that from the capacitance reading terminal 12, there is a capacitance of 4 due to the change in the depletion layer 8, a capacitance due to the insulating film 1] itself, and a P-type semiconductor. layer 1
.. The capacitance due to the N-type semiconductor layer 2 is added in series, and the series capacitance is calculated.
上記絶縁膜11としてはシリコン酸化膜を一例に挙げた
が誘電体材料であれば任意の獅料を使用することができ
る。As the insulating film 11, a silicon oxide film is taken as an example, but any dielectric material can be used.
また各半導体層はシリコンを含む任意の半導体材料によ
って構成することができ、さらに各半導体層゛ の導電
型は任意に選択すらことができる。Furthermore, each semiconductor layer can be made of any semiconductor material including silicon, and the conductivity type of each semiconductor layer can even be arbitrarily selected.
以上述べて明らかなように本発明によれば、PN接合部
を形成する一方側の半導体層にオーミック電極7゛ら成
る第11!−極”よび竺縁膜な介してMO8構造から成
る第2電極を各々設け一1上記第1電極を空続出用端子
とし上用いるように構成するものであるから、空乏層側
−、、鼠バイアス端子と容量読出用端子とを直流的に独
立Sせることができる。 −したがって、同調回路
等に適用した場合でも入力信号の影響によって同調ずれ
等を生じることはなくなるので、広範囲の用途に適用で
きるようKなる。As is clear from the above description, according to the present invention, the ohmic electrode 7 is formed on the semiconductor layer on one side forming the PN junction. - A second electrode of MO8 structure is provided through the electrode and the edge film, respectively. Since the first electrode is configured to be used as a terminal for connecting air, the depletion layer side is The bias terminal and the capacitance readout terminal can be made independent in terms of direct current. - Therefore, even when applied to a tuned circuit, etc., there will be no tuning deviation due to the influence of the input signal, so it can be applied to a wide range of applications. I will be able to do it.
特に本発明のように絶、縁膜を介して容量続出電極を設
けることにより、リーク電1流を少なく抑えることがで
きるのでより高性能な・、動作が期待できる。In particular, by providing a continuous capacitive electrode via an insulating film as in the present invention, the leakage current can be suppressed to a low level, so higher performance operation can be expected.
第1図および第2図はそれぞれ従来例および本発明実施
例を示す、断面図である。 2−3・・・PN接合部、
6・・・空乏層制御用ノくイアスミ圧、8・・・空乏層
、9・・・・オーミ・ツク電極(空、乏、層制御・(イ
、1アス電極)、10・・・容量読出電極1.111・
・・・絶縁膜、12・・・容量読出用端子。
・ 特許出願人 クラリオン株式会社ゝ 。
第1囮
第2囚FIG. 1 and FIG. 2 are sectional views showing a conventional example and an embodiment of the present invention, respectively. 2-3...PN junction,
6... Insulator pressure for controlling depletion layer, 8... Depletion layer, 9... Ohmic electrode (empty, depletion, layer control (A, 1 as electrode), 10... Capacity Readout electrode 1.111・
...Insulating film, 12...Capacitance reading terminal.・Patent applicant: Clarion Co., Ltd. 1st decoy 2nd prisoner
Claims (1)
に接してPN接合一部を、形成する第2導電型半導体層
と、この第2導電型半導体層に設けられた第1電極およ
び第2導電型半導体層に絶縁膜を介して設けられた第2
電極とを含み、上記第1電極がi2層制御用バイアス端
子として用いられかつ上記第2電極が容量続出用端子と
して用いられるように構成したことを特徴とする可変容
量素子。 2、゛上記絶縁膜がシリコン酸化膜から成ることを特徴
とする特許請求の艷囲゛第・1項記載の可変容量素子。[Claims] 1. a first conductivity type semiconductor layer; A second conductive type semiconductor layer that forms a part of a PN junction in contact with the first conductive type semiconductor layer, and an insulating film on the first electrode provided on the second conductive type semiconductor layer and the second conductive type semiconductor layer. the second provided through
1. A variable capacitance element comprising: an electrode, the first electrode being used as an i2 layer control bias terminal, and the second electrode being used as a capacitance successive terminal. 2. The variable capacitance element according to claim 1, wherein the insulating film is made of a silicon oxide film.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14096781A JPS5843579A (en) | 1981-09-09 | 1981-09-09 | Variable capacity element |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14096781A JPS5843579A (en) | 1981-09-09 | 1981-09-09 | Variable capacity element |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5843579A true JPS5843579A (en) | 1983-03-14 |
Family
ID=15280982
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP14096781A Pending JPS5843579A (en) | 1981-09-09 | 1981-09-09 | Variable capacity element |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5843579A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5093694A (en) * | 1990-04-06 | 1992-03-03 | Ueyama Ken Ichi | Semiconductor variable capacitance diode with forward biasing |
-
1981
- 1981-09-09 JP JP14096781A patent/JPS5843579A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5093694A (en) * | 1990-04-06 | 1992-03-03 | Ueyama Ken Ichi | Semiconductor variable capacitance diode with forward biasing |
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