GB2105106A - Variable capaciter - Google Patents

Abstract

In a variable capacitor which comprises a barrier 3 permitting generation of a depletion layer 8 and a semiconductive region 14/15 permitting growth of the depletion layer when reverse bias voltage is applied to the barrier, the sectional area of the semiconductive region for growth of the depletion layer varies with distance from the barrier 8. The barrier is provided by a P/N junction, an MIS arrangement or a Schottky junction. <IMAGE>

Description

SPECIFICATION Variable capacitor This invention relates to a variable capacitor so designed that capacitance is linearly variable in response to variation of reverse bias voltage.

It is well known to utilize as variable capacitor a p-n junction element as shown in Figure 1. In this Figure, the reference numeral 1 denotes an n-type semiconductor layer, 2 is a p-type semiconductor region, 3 is a p-n junction, 4 and 5 are electrodes disposed in said layer 1 and region 2, 6 and 7 are outgoing or lead-out terminals disposed for said electrodes 4 and 5, respectively, and 8 is a depletion layer spreading from the p-n junction 3 and mainly on one side of the n-type layer 1 where impurity concentration is low. In the above configuration of variable capacitor, the depletion layer 8 expands and contracts depending upon the reverse bias voltage applied to said lead-out terminals 6 and 7, then change of capacitance due to the expansion or contraction of the depletion layer 8 being readable between the lead-out terminals 6 and 7.

However, such conventional variable capacitor using a p-n junction element has following drawbacks: since expension of depletion layer becomes dull particularly when the reverse bias boltage is large, capacitance varies as if saturated as shown by solid line in Figure 2 instead of linear variation as shown by dotted line in the same graph, thereby limiting actuatable range of the variable capacitor when using it in an electronic tuning circuit, etc.

Accordingly, the present invention to overcome the above-mentioned drawbacks of the conventional field of technique concerning variable capacitors, by providing a variable capacitor having a barrier allowing generation of a depletion layer and a semiconductive region allowing growth of the depletion layer to vary sectional area of the semiconductive region as being apart from the barrier.

In accordance with the present invention, there is provided a variable capacitor which comprises: a semiconductive member having a barrier per mitting generation of a depletion layer and a semiconductive region permitting growth of the depletion layer therein; a depletion layer control electrode and a common electrode disposed at both ends of said semiconductive member; and a reverse bias voltage applying means for ap plying reverse bias voltage for said barrier to said both electrodes; said semiconductive region being so formed that sectional area thereof gradually varies as being apart from said barrier.

Examples of the present invention will now be described with reference to the accompanying draw ings in which: Figures 1 and 2 are sectional view and a character istic graph of a conventional variable capacitor; Figures 3 and 4 show the theory of the present invention of which (a) is a perspective schematic view, (b) is a sectional schematic view, and (c) is a schematic plan; Figures 5 and 6 are sectional views showing embodiments according to the present invention; Figure 7 is a characteristic graph for explanation of the present invention; and Figures 8 and 9 are sectional views of further embodiments according to the present invention.

Figures 3 and 4 show the theory of the present invention: (a) is a perspective schematic view; (b) is a sectional schematic view; and (c) is a schematic plan.

In these Figures, the reference numeral refers to a barrier in MIS structure or in a Schottkyjunction structure causing generation of a depletion layer, 10 to a semiconductive region made of a p-type or n-type semi-conductor permitting growth of the depletion layer, 11 to a depletion layer control region consisting of a reversely conductive semiconductive region or an insulator for restricting growth of the depletion layer. Numeral 12 denotes a capacitance read-out section and 13 is an ohmic electrode disposed on the semiconductive region 10.

With this arrangement, when reverse bias voltage is applied to the barrier 9, the depletion layer grows in the semiconductive region 10 and spreads along with increase of the reverse bias voltage. In this case, the depletion layer which has reached the boundary of the depletion layer control region 11 which is in contact with the semiconductive region 10 is prevented from spreading into the depletion layer control region and spreads only in the semiconductive region 10. This means it is possible to govern how to spread the depletion layer in response to the reverse bias by adequately designing the configuration at the boundary. Capacitance between the capacitance read-out section 12 and the ohmic electrode 13 is determined depending upon configuration of the depletion layer and positional relative between the end of the depletion layer and the capacitance read-out section.

The present invention utilizes the abovementioned theory as to growth of the depletion layer.

Figures 5 and 6 are sectional and perspective views showing practical structure of an emboidment of the variable capacitor according to the present invention.

In these Figures, numeral 14 refers to a p-type semiconductive region, 15 to an n-type semiconductive region which is in contact with the p-type semiconductive region, 16to an insulatorsurrounding those regions 14 and 15, 17 and 18 to a depletion layer control electrode and a common electrode disposed in those regions 14 and 15, respectively.

The p-n junction 3 is formed perpendicularly of thickness direction of the semiconductive region in Figure 5 while it is formed horizontally of length direction of the semiconductive region in Figure 6. In both cases, impurity concentration of the p-type semiconductive region wherein the depletion layer is to grow is determined lower than that of the n-type semiconductive region 15 and the configuration of the p-type semiconductive region 14 is so designed that sectional area thereof becomes smaller and smaller as coming apart from the p-n junction 3. To make the sectional area smaller and smaller, dis tance between the boundaries 19 of the insulator 16 and the p-type semiconductive region 14 may be designed to be narrowed as getting apart from the p-n junction 3, by curving the boundary lines, for example.

Under that condition, when reverse bias voltage is applied to the electrodes 17 and 18 so as to reversely bias the p-n junction, the depletion layer 8 grows from the p-n junction mainly in the p-type semiconductive region 14 wherein impurity concentration is low. At that time, since the depletion layer expands along the curved boundary lines 19 even upon high reverse bias voltage, the expansion becomes acute and not dull as seen in conventional variable capacitors.Namely, since electric charge which is charged in the p-type semiconductive region 14 due to reverse bias voltage and space charge which generates in the depletion layer based upon said electric charge in the p-type semiconductive region 14 keep balance substantially of one-by-one, when high reverse bias voltage is applied, the depetion layer 8 comes to expand in the p-type semiconductive region 14 which is narrowed by the curved boundaries 19. Therefore, the depletion layer can expands widely, thus representing large capacitance variation.

Referring to Figure 7 showing capacitance characteristic, it is noted that the capacitance variation is not saturated even when reverse bias voltage is high.

Configuration of the semiconductive region as shown in Figures 5 and 6 may be easily formed by modifiying conditions of widely used diffusion technique and it is also possible to determine the configuration as desired according to purposes.

Beside these, any kind of semiconductive region and depleton layer control region may be selected as desired.

Figures 8 and 9 show further embodiments according to the present invention wherein there is provided a capacitance read-out section 20 includes an electrode 21 disposed astride the semiconductive regions 14 and 15. The capacitance read-out section 20 is configured of well-known p-n junction struc ture, MIS structure of Schottkyjunction structure.

Accordingly to this embodiment, particularly, capacitance veriation which is controlled by reverse bias voltage applied between the depletion layer control electrode 17 and the common electrode 18 is read out by a capacitance read-out terminal R2 disposed between the capacitance read-out electrode 21 and the common electrode 18. Interrelation between reverse bias voltage and capacitance is as shown in Figure 7 wherein capacitance variation is not saturated even when the reverse bias voltage is high.

As described in the above, a variable capacitor according to the present invention comprises a barrier for generation of a depletion layer and a semiconductive region for growth of the depletion layer and the semiconductive layer wherein the depletion layer is to expand is designed to become narrow as being apart from the barrier. This leads to increase of capacitance variation at the time of increase of reverse bias voltage, thus obtaining linear capacitance variation in response to variation of reverse bias voltage. Therefore, when using the variable capacitor in an electronic tuning circuit, it is possible to get a wide actuatable range and to improve performance of the electronic tuning circuit.

Claims (8)

1. A variable capacitor which comprises: a semiconductive member having a barrier permitting generation of a depletion layer and a semiconductive region permitting growth of the depletion layer therein; a depletion layer control electrode and a common electrode disposed at both ends of said semiconductive member; and a reverse bias voltage applying means for applying reverse bias voltage for said barrier to said both electrodes; said semiconductive region being so formed that sectional area thereof gradually veries as being apart from said barrer.

2. A variable capacitor of Claim 1 further comprising a capacitance read-out section disposed in said semiconductive region.

3. A variable capacitor of Claim 1 further comprising a capacitance read-out terminai disposed between said depletion layer control electrode and said common electrode.

4 A variable capacitor of Claim 2 further comprising a capacitance read-out terminal disposed between said common electrode and said capacitance read-out section.

5. A variable capacitor of one of Claims 1 through 4 further comprising an insulator so disposed to surround said semiconductive region.

6. A variable capacitor of one of Claims 1 through 5 in which said semiconductive region comprises a p-type semiconductive region having a p-n junction and an n-type semiconductive region.

7. A variable capacitor of Claim 6 in which said semiconductive region to grow said depletion layer is configured in said p-type semiconductive region having a lower impurity concentration than that of said n-type semiconductive region and said p-type semiconductive region is so formed that sectional area thereof becomes smaller as being apart from said p-n junction.

8. A variable capacitor substantially as hereinbefore described with reference to and as illustrated in Figures 3 to 9 of the accompanying drawings.