JPS6046077A - Variable capacitance element - Google Patents
Variable capacitance elementInfo
- Publication number
- JPS6046077A JPS6046077A JP15397783A JP15397783A JPS6046077A JP S6046077 A JPS6046077 A JP S6046077A JP 15397783 A JP15397783 A JP 15397783A JP 15397783 A JP15397783 A JP 15397783A JP S6046077 A JPS6046077 A JP S6046077A
- Authority
- JP
- Japan
- Prior art keywords
- film
- insulating film
- ratio
- insulating
- capacitance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 150000004767 nitrides Chemical class 0.000 claims description 3
- 230000006866 deterioration Effects 0.000 abstract description 3
- 238000009413 insulation Methods 0.000 abstract description 3
- 239000012535 impurity Substances 0.000 abstract description 2
- 230000000873 masking effect Effects 0.000 abstract description 2
- 230000002542 deteriorative effect Effects 0.000 abstract 1
- 230000009545 invasion Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 210000003127 knee Anatomy 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/92—Capacitors with potential-jump barrier or surface barrier
- H01L29/93—Variable capacitance diodes, e.g. varactors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/92—Capacitors with potential-jump barrier or surface barrier
- H01L29/94—Metal-insulator-semiconductors, e.g. MOS
Abstract
Description
【発明の詳細な説明】
本発明は、太ぎな容量変化比が得られるようになされた
可変容量素子に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a variable capacitance element capable of obtaining a large capacitance change ratio.
電子同調ラジオ等に使用される可変容量素子として従来
第1図のようなPN接合ダイオードが知られている。A PN junction diode as shown in FIG. 1 is conventionally known as a variable capacitance element used in electronically tuned radios and the like.
同図において1はN型半導体領域、2はP型半導体領域
、3はPN接合、4および5は上記領域1および領域2
に各々設けられたオーミック電極6および7は上記電極
4,5に各々設けられた引出し端子、8は空乏層である
。以上の構成において、引出し端子6および7に加えら
れるバイアス電圧に応じて空乏層8が伸縮し、これに基
づ(容量値の変化が上記引出し端子6および7間におい
て読み出されるようになっている。In the figure, 1 is an N-type semiconductor region, 2 is a P-type semiconductor region, 3 is a PN junction, and 4 and 5 are the above regions 1 and 2.
Ohmic electrodes 6 and 7 provided on the electrodes 4 and 5 are lead terminals provided on the electrodes 4 and 5, respectively, and 8 is a depletion layer. In the above configuration, the depletion layer 8 expands and contracts in accordance with the bias voltage applied to the lead terminals 6 and 7, and based on this, the change in capacitance value is read out between the lead terminals 6 and 7. .
ところでこのような構造の可変容量素子においては、上
記引き出し端子6および7が容量読出し端子(電極)と
して用いられると共にを2層8ン伸縮さセるためのバイ
アス電圧印加端子としても用いられるために、引出し端
子6および7間に容量続出用人力信号が印加されに時あ
るいはバイアス電圧が印加された時は共に空乏層8が伸
縮するので容量値が変化音ることになる。このために同
調回路に適用した場合には入力信号によって容量値が変
化してしまうので、同調ずれが生ずるようKなり、また
混変調特性の劣化の原因となる。すなわち入力信号によ
って容量変化を受けしかもその変化曲線は非線形となる
ので1人力信号周波数が変調ン受けて高周波成分が生ま
れるようになる。By the way, in the variable capacitance element having such a structure, the lead terminals 6 and 7 are used not only as capacitance readout terminals (electrodes) but also as bias voltage application terminals for expanding and contracting the two layers. When a human input signal for increasing the capacitance is applied between the extraction terminals 6 and 7, or when a bias voltage is applied, the depletion layer 8 expands and contracts, resulting in a change in the capacitance value. For this reason, when applied to a tuning circuit, the capacitance value changes depending on the input signal, causing tuning deviation and deterioration of cross-modulation characteristics. That is, since the capacitance changes depending on the input signal and the change curve becomes non-linear, the frequency of the input signal is modulated and a high frequency component is generated.
このような欠点ン除くために容量読出し電極とバイアス
電圧印加電極とン分離させるように構成した。第2図(
aJのような3端子のMIS型可変可変容量素子開昭5
5−120175号公報で示されるように提供されてい
る。In order to eliminate such defects, the capacitance readout electrode and the bias voltage application electrode are separated from each other. Figure 2 (
3-terminal MIS type variable capacitance element like aJ
No. 5-120175.
同図において、11はN型半導体領域+ 12A、 1
2BはP型半導体領域、13はPN接合、14は上記P
+型領域12A、128間のN型領域11表面に設けら
れ几絶縁膜、 15.16A、 16 B、 17は各
々N型領域11゜P1型領域12A、12B、絶縁膜1
4に設けられた電極。In the same figure, 11 is an N-type semiconductor region + 12A, 1
2B is a P-type semiconductor region, 13 is a PN junction, and 14 is the above P
A dielectric film 15, 16A, 16B, and 17 are provided on the surface of the N-type region 11 between the +-type regions 12A and 128, respectively.
Electrode provided at 4.
18、19.206’!各々電極15.電極16A、1
6B、電極17に設けられU引出し端子、21は空乏層
である。18, 19.206'! Each electrode 15. Electrode 16A, 1
6B is a U lead terminal provided on the electrode 17, and 21 is a depletion layer.
上記P型領域12A、12Bおよびこれらに設けられた
電極16A、16Bによって空乏層制御部幻が構成され
、絶縁膜14およびこれに設けられた電極17によって
容量読出部列が構成される。The P-type regions 12A, 12B and the electrodes 16A, 16B provided thereon constitute a depletion layer control section, and the insulating film 14 and the electrodes 17 provided thereon constitute a capacitive readout section array.
以上において引出しん子18.19間にPN接合13ン
逆バイアスするようなバイア2電圧vBン印加しこれを
可変することによりを2層21の幅が変化し、それによ
る容量変化が引出し端子18.20間から読み出されて
第2図(bJのような容量(CJ対箪圧(VJ特性が得
られる。ここで容量Hは上記逆バイアス電圧vBが00
時の値であり、容量りは逆バイア7、電圧vBが増加さ
れしぎい電圧VBTl”経過しに後の、 VBL時にお
ける値であり、各々Mis−C−V特性における容量最
大値CmaXおよび容量最小値Cm1nを示している。In the above, the width of the second layer 21 is changed by applying a voltage vB to the via 2 which reverse biases the PN junction 13 between the lead terminals 18 and 19, and changing this voltage. The capacitance (CJ vs. pressure (VJ) characteristics as shown in Figure 2 (bJ) can be obtained by reading from between .20 and 20.
The capacitance is the value at VBL after reverse bias 7, the voltage vB is increased and the threshold voltage VBTl has passed, and the capacitance is the maximum value CmaX and the capacitance in the Mis-C-V characteristics, respectively. The minimum value Cm1n is shown.
ここで第2図(aJの構造で可変容量素子としての容量
変化比を大きくするためには上記H/L比を太きくする
必要がある。この要望を満たすための手段としては上記
容量読出部24ケ構成している絶縁膜14の膜厚ン小に
する方法、あるいはN型半導体領域11のキャリア濃度
7丁げろ方法が考えられる。Here, in order to increase the capacitance change ratio as a variable capacitance element with the structure of FIG. 2 (aJ), it is necessary to increase the above H/L ratio. A method of reducing the thickness of the 24 insulating films 14, or a method of reducing the carrier concentration of the N-type semiconductor region 11 by 7 points can be considered.
しかし後者のように、キャリア濃度ン下げることはQ値
の低下ン招(ので好筐しくない。 !また前者において
は第3図に示すように、tfJ軸の絶縁膜14例えば酸
化膜の膜厚tを/J1にする程縦軸のH/L比を大きく
することができる力瓢それに比例して絶縁膜14内のピ
ンホール数が増加してくる等に因って絶縁膜14の絶縁
性が劣化して(るのは避けられない。However, as in the latter case, lowering the carrier concentration is not desirable because it leads to a decrease in the Q value. Also, in the former case, as shown in FIG. As t becomes /J1, the H/L ratio on the vertical axis can be increased, and the number of pinholes in the insulating film 14 increases proportionally, so the insulating property of the insulating film 14 increases. It is inevitable that the
本発明は以上の問題に対処してなされKもので、半導体
基板上に空乏層制御部と絶縁膜を介して設げられ定容量
読出電極を含む容量読出部とが形成されてなる可変容量
素子において、上記絶縁膜が半導体基板表面に形成され
た第1の絶縁膜およびこの上に形成された第2の絶縁膜
の積層構造に構成することにより従来欠点を除去するよ
うにした可変容量素子を提供することを目的とするもの
である。以下図面を参照して本発明実施例を説明する。The present invention has been made in response to the above problems, and is a variable capacitance element in which a depletion layer control section and a capacitance readout section including a constant capacitance readout electrode are formed on a semiconductor substrate via an insulating film. A variable capacitance element is provided in which the insulating film has a laminated structure of a first insulating film formed on the surface of a semiconductor substrate and a second insulating film formed thereon, thereby eliminating the conventional drawbacks. The purpose is to provide Embodiments of the present invention will be described below with reference to the drawings.
第4図は本発明実施例による可変容量素子を示す断面図
で第2図(a)と同一部分は同一番号で示し、容量続出
部冴を構成する絶縁膜δはN型半導体領域11表面に形
成きれた第1の絶縁膜25A例えば酸化膜(5i02
)およびこの上に形成された第2の絶縁膜25B例えば
窒化膜(SiN )からなる積層構造によって構成され
る。FIG. 4 is a cross-sectional view showing a variable capacitance element according to an embodiment of the present invention. The same parts as in FIG. The fully formed first insulating film 25A, for example, an oxide film (5i02
) and a second insulating film 25B formed thereon, for example, a nitride film (SiN 2 ).
H7L比のHレベルおよびLレベルは次の式によって絡
えられる。The H level and L level of the H7L ratio are related by the following equation.
Hレベル:
Lレベルニ
ー例トシて、dSio2=100 A + dS tN
”” 100 Aに設定した時、上記(17,(2J
に基つ(計算の結果、H7L比は約41@を得ることが
でき瓦。これはdsiQ2= 100^で酸化#25A
のみ設けた場合のH/L比よりやや/J%さな値である
が、絶縁性の点では著るしく医れておりしかもdsi0
2ユ1,000λに単独に設けた場合に比べて約5陪の
値となる。H level: L level knee example, dSio2=100 A + dS tN
"" When set to 100 A, the above (17, (2J
(As a result of calculation, the H7L ratio can be obtained as approximately 41@.
Although the H/L ratio is a little lower than the H/L ratio when the
The value is about 5 times larger than that when it is provided alone at 2 U and 1,000 λ.
このように、容量読出部列の絶縁膜5を多層構造に構成
することにより、下部の絶縁膜25Aの膜厚を小に設定
してもこれに因る絶縁性の劣化は上部の絶縁膜25Bに
より補われるので、絶縁性を劣化させることな(H/L
比を大きくとることができるようになる。As described above, by configuring the insulating film 5 of the capacitive readout section column to have a multilayer structure, even if the film thickness of the lower insulating film 25A is set to a small value, the deterioration of insulation due to this will be reduced to the upper insulating film 25B. Since it is compensated for by
You will be able to increase the ratio.
特に窒化膜は絶縁性に曖れていると共に外部からの有無
不純物等の侵入に対するマスク性にも浸れているので、
酸化膜と組み合わセることにより膜厚が小さくとも十分
大きなH/L比を得ることができる。In particular, nitride films have poor insulating properties and also have masking properties against the intrusion of impurities from the outside.
By combining it with an oxide film, a sufficiently large H/L ratio can be obtained even if the film thickness is small.
各絶縁膜の膜厚の設定は目的、用途に応じて任意に選ぶ
ことができる。The thickness of each insulating film can be arbitrarily selected depending on the purpose and application.
以上述べて明らかなように本発明によれば、半導体基板
上に空乏層制御部と絶縁膜を介して設けられ1こ容量読
出電極を含む容量続出部とが形成されてなる可変容量素
子において、上記絶縁膜が半導体基板表面に形成された
第1の絶縁膜およびこの上に形成された第2の絶縁膜の
積層構造に構成したものであるから、従来欠点を除去す
ることができる。As is clear from the above description, according to the present invention, in a variable capacitance element in which a depletion layer control section and a capacitance continuous section including a capacitance read electrode are formed on a semiconductor substrate through an insulating film, Since the insulating film has a laminated structure of the first insulating film formed on the surface of the semiconductor substrate and the second insulating film formed thereon, the conventional drawbacks can be eliminated.
本発明により容量変化比の大きな可変容量素子が得られ
るので、電子同調を必要とする各種同調回路に広範囲に
適用することかできる。Since the present invention provides a variable capacitance element with a large capacitance change ratio, it can be widely applied to various tuning circuits that require electronic tuning.
第1図、第2図(a)および第2図(bJは従来例を示
す断面図および特性図、第3図は本発明を説明するため
の特性図、第4図は本発明実施例を示す断面図である。
16A、16B・・・バイアス電極、17・・・容量読
出電極、21・・・空乏層、乙・・・空乏層制御部、冴
・・・容量続出部、25、25A、 25B−・・絶縁
膜。
第1図
一一二岬
り。
寸
11
F)
−H蘂
−LFigures 1, 2 (a) and 2 (bJ are cross-sectional views and characteristic diagrams showing a conventional example, Figure 3 is a characteristic diagram for explaining the present invention, and Figure 4 is a diagram showing an example of the present invention. 16A, 16B: Bias electrode, 17: Capacitance reading electrode, 21: Depletion layer, B: Depletion layer control section, Sae: Capacitance continuous section, 25, 25A , 25B--Insulating film. Figure 1 112 cape. Dimension 11 F) -H leg-L
Claims (1)
られた容量読出電極ン含む容量続出部とが形成されてな
る可変容量素子において、上記絶縁膜が半導体基板表面
に形成された第1の絶縁膜およびこの上に形成された第
2の絶縁膜の積層構造から構成されたことン特徴とする
可変容量素子。 2、 上記第1の絶縁膜が酸化膜および第2の絶縁膜が
窒化膜から構成されたことヲ4?徴とする特許請求の範
囲第1項記載の可変容量素子。[Claims] 1. A variable capacitance element in which a depletion layer control section and a capacitance continuous section including a capacitance read electrode provided through an insulating film are formed on a semiconductor substrate, wherein the insulating film is formed on a semiconductor substrate. A variable capacitance element characterized in that it has a laminated structure of a first insulating film formed on the surface and a second insulating film formed thereon. 2. The first insulating film is an oxide film, and the second insulating film is a nitride film. The variable capacitance element according to claim 1, characterized in that:
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15397783A JPS6046077A (en) | 1983-08-23 | 1983-08-23 | Variable capacitance element |
DE19843431053 DE3431053A1 (en) | 1983-08-23 | 1984-08-23 | Capacitor component having an adjustable capacitance |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15397783A JPS6046077A (en) | 1983-08-23 | 1983-08-23 | Variable capacitance element |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6046077A true JPS6046077A (en) | 1985-03-12 |
Family
ID=15574212
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP15397783A Pending JPS6046077A (en) | 1983-08-23 | 1983-08-23 | Variable capacitance element |
Country Status (2)
Country | Link |
---|---|
JP (1) | JPS6046077A (en) |
DE (1) | DE3431053A1 (en) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4835587A (en) * | 1984-09-19 | 1989-05-30 | Fuji Electric Co., Ltd. | Semiconductor device for detecting radiation |
US5254867A (en) * | 1990-07-09 | 1993-10-19 | Kabushiki Kaisha Toshiba | Semiconductor devices having an improved gate |
US6369671B1 (en) * | 1999-03-30 | 2002-04-09 | International Business Machines Corporation | Voltage controlled transmission line with real-time adaptive control |
-
1983
- 1983-08-23 JP JP15397783A patent/JPS6046077A/en active Pending
-
1984
- 1984-08-23 DE DE19843431053 patent/DE3431053A1/en not_active Withdrawn
Also Published As
Publication number | Publication date |
---|---|
DE3431053A1 (en) | 1985-03-14 |
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