KR20060075660A - Variable capacitor circuit having serially connected capacitors - Google Patents

Abstract

The variable series capacitor circuit according to the present invention controls the capacitance between the input and output nodes by connecting a plurality of capacitors in series between the input node and the output node and controlling the coupling between the capacitors between the input and output nodes with a switching transistor. Control of the turning on / off of the switching transistor is made through the decoder circuit. Preferably, the capacitor has a metal insulator metal (MIM) structure, and the capacitor has a structure in which a metal film and a dielectric film are stacked, and the metal film forming the electrode of the capacitor is preferably shared with the metal film of another capacitor. According to the present invention, the capacitance of a capacitor can be freely changed in an integrated circuit device, and in particular, when the capacitance of the capacitor needs to be changed during use, such as a frequency matching device or a variable frequency oscillation circuit, the input signal of the decoder is controlled. It is easy to change the capacitance of the capacitor to suit your needs, it is possible to freely change the capacitance of the capacitor without taking up a large area in the integrated circuit, and to change the variable series capacitor without significantly increasing the stack height. Can be implemented.

Capacitors, Variable Capacitors, Metal Insulator Metal (MIM)

Description

Variable Capacitor Circuit having Serially Connected Capacitors}

1 is a cross-sectional view of a capacitor having a conventional metal insulator metal (MIM) structure.

2 is a cross-sectional view of a capacitor of the MIM structure connected in series in accordance with the present invention.

3 is a circuit diagram showing the structure of a variable series capacitor circuit according to the present invention.

<Description of Major Symbols in Drawing>

10, 14, 18, 22, 26: metal film 12, 16, 20, 24: dielectric film

30: series capacitor

TECHNICAL FIELD The present invention relates to semiconductor technology, and more particularly, to a variable series capacitor circuit capable of arbitrarily adjusting a capacitor's capacity as needed.

In general, semiconductor capacitors integrated in integrated circuit (IC) devices have a metal insulator metal (MIM) structure using CMOS process technology. 1 is a cross-sectional view of a conventional MIM structure capacitor.

A capacitor of the conventional MIM structure forms a metal film 2, which is used as a first electrode of a capacitor, on a substrate (not shown), as shown in FIG. 1, and puts a dielectric film 4 (e.g., an oxide film) thereon and then the dielectric film ( 4) A metal film 6 to be used as the second electrode of the capacitor is formed above. Capacitance, which is an electrical characteristic of a capacitor, is determined by variables such as the thickness of the dielectric film 4 (ie, the distance between the metal films 4 and 6), the dielectric constant, and the area of the metal films 4 and 6. However, the conventional capacitor of FIG. 1 has a disadvantage in that all of these variables are fixed, so that the capacity of the capacitor needs to be redesigned accordingly and the manufacturing process must be newly made from the beginning.

In order to solve this problem, a plurality of capacitors of various capacities are made in advance in an integrated circuit, and then, depending on the required capacitance, a plurality of capacitors are selectively connected by using a fuse cutting method. It is not possible to change the capacity of a capacitor once set by use of the fuse. Therefore, it is difficult to apply in places such as a frequency matching device or a variable frequency oscillator circuit.

The present invention therefore provides a capacitor drive circuit that overcomes the limitations of such conventional capacitors and allows the capacity of the capacitors to be changed freely during use.

Another object of the present invention is to implement a plurality of variable capacitors without occupying a large area in the integrated circuit and without increasing the stack height.

The variable series capacitor circuit according to the present invention controls the capacitance between the input and output nodes by connecting a plurality of capacitors in series between the input node and the output node and controlling the coupling between the capacitors between the input and output nodes with a switching transistor. Control of the turning on / off of the switching transistor is made through the decoder circuit. Preferably, the capacitor has a metal insulator metal (MIM) structure, and the capacitor has a structure in which a metal film and a dielectric film are stacked, and the lower electrode of the second capacitor shares the upper electrode of the first capacitor stacked below the second capacitor. It is desirable to.

According to an embodiment of the present invention, a variable series capacitor circuit includes (A) a series capacitor unit in which a plurality of capacitors including a first capacitor and a second capacitor are connected in series, and (B) between the first capacitor and the output node. A plurality of switching transistors including a first switching transistor connected to the second capacitor and a second switching transistor connected between the second capacitor and the output node, the plurality of switching transistors controlling a plurality of capacitors to be connected between the input node and the output node, and (C ) A decoder to control turn on / off of the plurality of switching transistors. Here, the first capacitor is connected between the input node and the first node, the second capacitor is connected between the first node and the second node, the gate of the first switching transistor is connected with the first output terminal of the decoder, The source is connected to the first node, the drain is connected to the output node, the gate of the second switching transistor is connected to the second output terminal of the decoder, the source is connected to the second node, and the drain is connected to the output node. The turn on / off of the switching transistor is controlled according to the output of the decoder, and thus the capacitance between the input node and the output node is changed.

Embodiment

Hereinafter, specific embodiments of the present invention will be described with reference to the accompanying drawings.

2 is a partial cross-sectional view of a capacitor circuit according to the present invention.

A metal to be used as the lower electrode of the first capacitor C1 is coated on a substrate (not shown), and a pattern is formed in a predetermined length and width. The first dielectric layer 12 is formed on the patterned first metal layer 10 and patterned to have a predetermined length and width. The second metal film 14 is formed by patterning a metal film to be used as the upper electrode of the first capacitor C1 to have the same length and width as the first dielectric film 12 on the first dielectric film 12. In this way, the first capacitor C1 is formed.

The second metal film 14 serving as the upper electrode of the first capacitor C1 also serves as the lower electrode of the second capacitor C2, and the second dielectric film 16 and the third metal film are disposed on the second metal film 14. 18 is patterned to form second capacitor C2. Similarly to the first capacitor C1, the second capacitor C2 has the same length and width as that of the second dielectric film 16 and the third metal film 18.

A third capacitor C3 is formed by patterning the third dielectric layer 20 and the fourth metal layer 22 on the third metal layer 18, and the fourth dielectric layer 24 and the fourth dielectric layer 24 are formed on the fourth metal layer 22. The fifth metal film 26 is patterned to form a fourth capacitor C4.

When the metal films 10, 14, 18, 22, and 26 of the first to fourth capacitors C1 to C4 thus formed are connected to the contacts (nodes A, N1, N2, N3, and N4), the capacitors C1 to C4 are each All of them are connected in series. As shown in FIG. 2, since the series capacitor of the present invention shares one metal film with another capacitor adjacent to each other, only five metal films need to be formed while forming four capacitors. Therefore, not only can the stack height of the capacitors be reduced, but it is also suitable for high integration by occupying less board area than when the capacitors are connected in parallel. For example, four capacitors are separately formed and the connection is cut by a fuse, for example. Compared to the conventional control, the area occupied can be greatly reduced.

Aluminum, tungsten, or the like may be used as the metal film used in the present invention, and as the dielectric film, a silicon oxide film (SiO ₂ ), an ONO film (Oxide-Nitride-Oxide), a nitride oxide film (NO: Nitride-Oxide), or Ta ₂ O ₅ , Al ₂ O ₃ , BaTiO ₃ , SrTiO ₃ , Al ₂ O ₃ -HfO ₂ , HfO ₂ , and the like can be used. In addition, since the capacitance of each capacitor can be adjusted by adjusting the length and width of the metal films 14, 18, 22, and 26 formed with the same length as the dielectric film, the capacitance of the capacitor can be adjusted very easily.

3 is a circuit diagram of the variable series capacitor circuit device of the present invention.

The variable series capacitor circuit device 100 includes a series capacitor unit 30 in which four capacitors C1 to C4 are connected in series, a plurality of switching transistors TR1 to TR4 and a decoder 40.

The first capacitor C1 of the series capacitor section 30 is connected between the input node A and the first node N1, the second capacitor C2 is connected between the first node N1 and the second node N2, and the third capacitor C3 is The fourth node C4 is connected between the second node N2 and the third node N3, and the fourth capacitor C4 is connected between the third node N3 and the fourth node N4. The first source / drain of the first switching transistor TR1 is connected to the first node N1, the second source / drain is connected to the output node B, and the gate is connected to the first output O1 of the decoder 40. The first source / drain of the second switching transistor TR2 is connected to the second node N2, the second source / drain is connected to the output node B, and the gate is connected to the second output O2 of the decoder 40. The first source / drain of the third transistor TR3 is connected to the third node N3, the second source / drain is connected to the output node B, and the gate is connected to the third output O3 of the decoder 40. The first source / drain of the fourth transistor TR4 is connected to the fourth node N4, the second source / drain is connected to the output node B, and the gate is connected to the fourth output O4 of the decoder 40.

Therefore, the capacitor between the input node A and the output node B is controlled by controlling the on / off of the switching transistors TR1 to TR4 through the decoder output signals O1 to O4 whose values are determined by the input signals S1 and S2 of the decoder 40. The capacity can be selected as follows.

(1) When the input signal S1 = 0 and the input signal S2 = 0 (where "0" refers to the ground voltage and "1" refers to, for example, VDD)

Since the output O1 of the decoder is "1" and the remaining outputs O2 to O4 are "0", only the first switching transistor TR1 of the NMOS transistors is turned on and the remaining second to fourth switching transistors are turned off. Therefore, only the first capacitor C1 is connected between the input node A and the output node B, and thus the capacitance becomes C1.                     

(2) When input signal S1 = 0 and input signal S2 = 1

Since the outputs O1 and O2 of the decoder are "1" and O3 and O4 are "0", the first and second switching transistors TR1 and TR2 of the NMOS transistors are turned on and the third and fourth switching transistors are turned off. Therefore, the first capacitor C1 and the second capacitor C2 are connected in series between the input node A and the output node B, and thus the capacitance becomes (1 / C1 + 1 / C2).

(3) When input signal S1 = 1 and input signal S2 = 0

Since the outputs O1 to O3 of the decoder are "1" and the output O4 is "0", the first to third switching transistors TR1 to TR3 of the NMOS transistors are turned on and the fourth switching transistor TR4 is turned off. Accordingly, the first capacitor C1, the second capacitor C2, and the third capacitor C3 are connected in series between the input node A and the output node B, and thus the capacitance becomes (1 / C1 + 1 / C2 + 1 / C3). .

(4) When input signal S1 = 1 and input signal S2 = 1

Since all outputs O1 to O4 of the decoder become "1", all of the first to fourth switching transistors TR1 to TR4 are turned on. Thus, the capacity between the input node A and the output node B becomes (1 / C1 + 1 / C2 + 1 / C3 + 1 / C4).

As described above, according to the capacitor circuit of the present invention, the capacitance between the input node A and the output node B can be variously changed while using the capacitors C1 to C4 having fixed capacitances.

Although specific embodiments of the present invention have been described with reference to the drawings, this is intended to be easily understood by those skilled in the art and is not intended to limit the technical scope of the present invention. Therefore, the technical scope of the present invention is determined by the matters described in the claims, and the embodiments described with reference to the drawings may be modified or modified as much as possible within the technical spirit and scope of the present invention. For example, in the drawings, the four capacitors are connected in series. However, the number of capacitors can be further increased or decreased. In FIG. 3, the position of the input node (node A) is adjusted to adjust any one of the nodes N1 to N4. It is also possible to adjust to connect to.

According to the present invention, the capacitance of the capacitor can be freely changed in the integrated circuit device, and in particular, only controlling the input signal of the decoder even when the capacitance of the capacitor needs to be changed as necessary for use, such as a frequency matching device or a variable frequency oscillation circuit. Also, the capacitance of the capacitor can be easily changed to suit the needs.

In addition, using the variable series capacitor circuit according to the present invention, it is possible to freely change the capacitance of the capacitor without occupying a large area in the integrated circuit. In addition, when the series capacitor is a stacked structure, the series capacitor can be implemented without greatly increasing the stack height by sharing the metal film forming the electrode of one capacitor with the electrode of the upper capacitor.

Claims (3)

Variable series capacitor circuit, A series capacitor unit in which a plurality of capacitors including a first capacitor and a second capacitor are connected in series; A first switching transistor connected between the first capacitor and an output node and a second switching transistor connected between a second capacitor and an output node, wherein the plurality of capacitors are controlled to be connected between an input node and an output node. A plurality of switching transistors, A decoder controlling turn on / off of the plurality of switching transistors, The first capacitor is connected between an input node and a first node, and a second capacitor is connected between the first node and a second node, The gate of the first switching transistor is connected to the first output terminal of the decoder, the source is connected to the first node, the drain is connected to the output node, and the gate of the second switching transistor is connected to the second output terminal of the decoder. The source is connected to the second node, the drain is connected to the output node, And the capacitance of the switching node is controlled according to the output of the decoder, and the capacitance between the input node and the output node is changed accordingly. In claim 1, And each of the plurality of capacitors has a metal insulator metal (MIM) structure. In claim 1, Wherein the first capacitor and the second capacitor have a MIM structure, and wherein an upper electrode of the first capacitor shares a lower electrode of the second capacitor.

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