FR2509093A1 - VARIABLE CAPACITOR - Google Patents

Abstract

THE PRESENT INVENTION RELATES TO A VARIABLE CAPACITOR. ACCORDING TO THE INVENTION, IT INCLUDES A SEMICONDUCTOR SUBSTRATE HAVING A BARRIER FOR PRODUCING A DIELECTRIC LAYER 8 ON A SURFACE OF THE SAME; A CAPACITY READING SECTION 17 PROVIDED ON A LATERAL SURFACE 11 OF THE SEMICONDUCTOR SUBSTRATE; A DIELECTRIC LAYER CONTROL SECTION 12 PROVIDED ON THE OPPOSITE SURFACE OF THE SEMICONDUCTOR SUBSTRATE; AND A REVERSE POLARIZATION MEANS V TO REVERSE POLARIZE THE DIELECTRIC LAYER CONTROL SECTION. THE INVENTION APPLIES IN PARTICULAR TO VARIABLE CAPACITORS HAVING THREE TERMINALS OR A CAPACITY READING SECTION IS SHAPED ON A SIDE SURFACE OF A SEMICONDUCTOR PELLET.

Description

The present invention relates to a condensation

  a three-terminal variable terminal having a capacitance reading section is provided on a lateral surface of a

semiconductor chip.

  It is well known to use, as a variable capacitor, a junction element A-1 as represented in FIG. 1. In this figure, the reference numeral 1 denotes a N-type semiconductor layer; the mark 2 is a semiconductor region of the type A; the mark 3 is a junction p-n; the marks 4 and 5 designate electrodes disposed in the layer 1 and the region 2 respectively; the pins 6 and 7 are output terminals which are arranged for the electrodes 4 and 5, respectively; and the mark 8 is a dielectric layer which extends from the Un junction 3 and mainly on one side of the N-type layer 1 with a low impurity concentration. In the above configuration of the variable capacitor, the dielectric layer 8 expands and contracts according to the bias voltage applied to the output terminals 6 and 7, the capacitance change due to the expansion or contraction of the dielectric layer 8 being read between the terminals of

Exit 6 and 7.

  However, conventional variable capacitors

  or the prior art using the junction elements mentioned above, have the following drawbacks: (1) As the dependence on the bias voltage of the capacitance of the dielectric layer in the p-junction is used. -_, the minimum capacity depends on the

  concentration of impurity in the semi-

  driver, while the maximum capacity depends on the increase of the conductive component Thus, it is practically impossible to obtain a significant change of the capacitance in a state where Q is important, and as the change of Q is more important with the change capacity, this presents a difficulty for the design

circuits.

  2 v 2509093 (2) As it is at the common output terminal that the bias voltage is applied for the capacitance change and the capacitance change is read, when these variable capacitors according to the prior art are employed in resonant circuits or the like, the voltage of the input signal itself easily induces an unnecessary change in capacitance, resulting in signal degradation Moreover, as a -configuration

  circuit is necessary to reduce the

  As between the voltage of the input signal and the bias voltage, such variable capacitors according to the prior art can be used only in a limited range of applications. (3) The concentration of the impurity in the semiconductor regions is controlled by the diffusion method or the ion implantation method, for the determination of the capacity of the dielectric layer; in general, however, as this process allows only a weak

  percentage available, the variable capacitors

  can not, in practice, be formed into one

integrated circuit.

  Accordingly, it is a primary object of the present invention to overcome the above-mentioned disadvantages of the conventional-technique relating to variable capacitors, by providing a variable capacitor where the capacitance reading section is provided on a lateral surface of a substrate. having a barrier formed by a dielectric on a surface, thereby increasing the capacitance variation without substantially increasing

  the surface of the reading section has capacity.

  According to the present invention there is provided a variable capacitor which comprises: a semiconductor substrate having a barrier for producing a dielectric layer on a surface; a capacitance reading section provided on a side surface of the semiconductor substrate; a dielectric layer control section provided on the opposite surface of the semiconductor substrate; and reverse bias means for biasing,

  in reverse, the dielectric layer control section.

  The invention will be better understood, and other purposes, features, details and advantages thereof

  will become clearer during the description

  explanatory text which follows with reference to the accompanying schematic drawings given solely by way of example illustrating several embodiments of the invention and in which: Figure 1 is a sectional view showing a variable capacitor according to the prior art; and Figures 2 to 5 are sectional views

  showing preferred embodiments according to the invention.

  FIG. 2 is a sectional view showing an embodiment according to the invention, where the reference numeral 9 designates

  a layer of the born type, the reference 10 a layer of the type -

  formed on the layer 9 of the n + type and the reference numeral 11 designates a lateral surface of the layer of the type, which is

  inclined e degrees relative to the junction ú N 3.

  On the other hand, the mark 12 designates a dielectric layer control electrode which is provided along the n + type layer 9, the mark 13 designates a capacitance reading section provided on the lateral surface 11 and comprising a reading electrode of FIG. capacity that will be described later The reference 14 designates a common electrode

  and the mark 15 an isolation layer.

  The capacitance reading section 13 may be formed at a pn junction configuration, selectively forming an N-type region 16 on the side surface 11 and forming a capacitance reading electrode 17 along the N-type region 16 as shown in FIG. 3, in an MIS configuration, forming the capacitance reading electrode 17 on the side surface 11 along the insulating layer 15 as shown in FIG. 4 or a Schottky junction configuration, providing for a metal 18 capable of forming a Schottky barrier and

  which can serve as a capacitance reading electrode.

  With this arrangement, when the polarization voltage

  VR is applied between the dielectric layer control electrode 12 and the common electrode 14, the dielectric layer 8 begins to expand from the junction À-n 3 mainly in the layer 10 of the type A, where the concentration of impurity is low, depending on the increase of the reverse bias voltage and the thickness d of the dielectric layer 8 increases At the same time, the length D of the dielectric layer 8 along the slope A of the side surface 11 also increases while the length B of the part on the lateral surface 11 which is

  not in contact with the dielectric layer 8, is gradually

reduced.

  In other words, when the reverse bias voltage VR is varied, the thickness of the dielectric layer 8 expands or contracts to

  thus vary its length D along the lateral surface 11.

  Therefore, the length B along the side surface 11 can also be controlled to thereby increase or decrease its area in response to a change in the surface area of the dielectric layer.

  be obtained between the reading electrode of capacity 17 or-

  18 and the p-type layer 10 from the surface corresponding to the length B. Moreover, between the capacitance reading electrode 17 or 18 and the ns-type layer 9, the capacitance C obtained is obtained by connecting in series C capacitance obtained above and the capacitance C 2 between the upper and lower plates of the dielectric layer 8 and by connecting more in parallel these two capacitors C 1 and C 2 to the capacitance C 3 produced between the electrode of capacity reading 17 or 18 and layer 9 of the n + type, by the zone corresponding to the length mentioned above D

(C = C 3 + C 1 C 2 / C 1 + C 2)

  As a result, there is a capacitance variation between the capacitance reading electrode 17 or 18 and the common electrode 14, thereby reducing the length B as the thickness of the dielectric layer is increased. capacitive variation which is read at the capacitance reading section R 1 between the capacitance reading electrode 17 or 18 and the common electrode 14 becomes weaker and therefore the capacitance variation corresponding to the variation of the reverse bias voltage This means that the capacitance variation that is read at the capacitance reading section R 1 between the capacitance reading electrode 17 or 18 and the common electrode 14 is controlled by the reverse bias voltage applied between the Dielectric layer control electrode 12 and common electrode 14 It should be noted that the capacitance which is read at a capacitance reading section R 2 between the capacitance reading electrode 17 or 18 and the dielectric layer control electrode 12 is also controlled by the reverse bias voltage VR. On the other hand, the capacitance that is read at the capacitance reading electrode 17 or 18 includes the capacitance by the insulating layer. 15

  in addition to that due to dielectric layer 8.

  When it is assumed that the slope angle of the lateral surface 11 is G degrees, the effective area of the capacitance reading electrode 17 or 18 can reach 1 / sin G times the horizontal surface. a pellet having the same horizontal surface, it is possible to obtain a greater variation of capacitance. This means that to obtain the same variation in capacitance, it is possible to use a smaller pellet. It is clear that the lower the angle G, Even more important is the effectiveness of the present invention. However, G can be determined

advantageously case by case.

  Such an angle G of the lateral surface 11 can

  be easily formed by an anisotropic attack method.

6 2509093

  The barrier for forming the control electrode 18 of the dielectric layer and for producing the dielectric layer 8 can be formed in MIS configuration or in

  Schottky junction configuration instead of configuring

  junction connection has adopted in the embodiment above. The variable capacitor having three terminals as described above can simultaneously be assembled during manufacture of an integrated circuit for a circuit

  electronic agreement at the end with a radio-

  This means that conventional integrated circuit processes can be used. However, in the prior art, since it was difficult to simultaneously form a variable capacitor during the fabrication of the integrated circuit, it was necessary to connect a capacitor. variable capacitor, made

separately, to the tuning circuit.

  As is apparent from the above, the present invention is arranged to increase the capacitance variation without substantially increasing the horizontal surface of the capacitance reading section by using a semiconductor substrate having a barrier to produce a dielectric layer on a surface and forming the capacitance reading section on the lateral surface of the substrate, allows for an easier increase in capacitance compared to the case of simply using the capacity of the horizontal dielectric layer by a reverse bias voltage. elsewhere, because

  structures of the control section of the dielectric layer

  of the capacitance reading section having three independent terminals, it is possible to eliminate the undesired influence due to the input signal Moreover, since the capacitance of the dielectric layer is not determined solely by the impurity concentration of the semiconductor region, no complicated means for precisely controlling the impurity concentration is required, resulting in an integrated circuit fabrication -with a

good performance.

Claims (8)

R E V E N D I C A T IO N S   A variable capacitor, characterized in that it comprises: a semiconductor substrate having a barrier for producing a dielectric layer (8) on one of its surfaces; a capacitance reading section (17; 18) provided on a side surface (11) of said semiconductor substrate; a dielectric layer control section (12) provided on the opposite surface of said substrate; and   a means of inverse polarization (VR) for polarity   riser, in reverse, said dielectric layer control section. 2. Variable capacitor according to claim 1, characterized in that it further comprises an electrode   joint (14) provided on the surface of the semi-   driver. 3. Variable capacitor according to any one   of claims 1 or 2, characterized in that the surface Lateral side is sloping.   4. Variable capacitor according to any one   claims 1, 2 or 3, characterized in that   further comprises a first capacitance read terminal which is provided between the aforementioned read section of   capacitance and dielectric layer control section.   5. Variable capacitor according to any one   claims 1, 2 or 3, characterized in that   further comprises a second capacitance reading terminal provided between the aforementioned capacitance reading section and the aforementioned common electrode -   6. Variable capacitor according to any one   claims 3, 4 or 5, characterized in that the   said semiconductor substrate comprises an n + type layer (9) and a p-type layer (10) on said n + type layer, and that said sloping side surface is formed along said p-type layer. 7. Variable capacitor according to any one   claims 1, 2, 3 or 6, characterized in that the   Ability reading section above is made in MIS configuration. 8. Variable capacitor according to any one   claims 1, 2, 3 or 6, characterized in that the   The aforementioned capacitance reading section is made in junction configuration 2-_ 9 Variable capacitor according to any one of   claims 1, 2, 3 or 6, characterized in that the   reading section of aforementioned ability is made in -   Schottky junction configuration. I