FR2458907A1 - Field effect transistor with adjustable pinch off voltage - has doping chosen in intermediate layer to reduce effect of parasitic bipolar transistor - Google Patents
Field effect transistor with adjustable pinch off voltage - has doping chosen in intermediate layer to reduce effect of parasitic bipolar transistor Download PDFInfo
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- FR2458907A1 FR2458907A1 FR7914991A FR7914991A FR2458907A1 FR 2458907 A1 FR2458907 A1 FR 2458907A1 FR 7914991 A FR7914991 A FR 7914991A FR 7914991 A FR7914991 A FR 7914991A FR 2458907 A1 FR2458907 A1 FR 2458907A1
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- 230000005669 field effect Effects 0.000 title claims abstract description 23
- 230000003071 parasitic effect Effects 0.000 title claims abstract description 13
- 230000000694 effects Effects 0.000 title abstract 2
- 238000001465 metallisation Methods 0.000 claims abstract description 13
- 230000010287 polarization Effects 0.000 claims description 9
- 238000002513 implantation Methods 0.000 claims description 3
- 150000002500 ions Chemical class 0.000 claims description 2
- 230000004048 modification Effects 0.000 claims description 2
- 238000012986 modification Methods 0.000 claims description 2
- 238000005468 ion implantation Methods 0.000 abstract description 4
- 238000000034 method Methods 0.000 abstract 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000008188 pellet Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0873—Drain regions
- H01L29/0878—Impurity concentration or distribution
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
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Abstract
Description
La présente invention concerne un transistor à effet de champ diffusé à grille isolée de tension de seuil ajustable. The present invention relates to a diffused field effect transistor with an insulated gate of adjustable threshold voltage.
Un transistor à effet de champ diffusé à grille isolée (DMOS) est un dispositif semiconducteur à trois électrodes comprenant essentiellement des régions ou couches de source et de drain de même type de conductivité et une région intermédiaire du type de conductivité opposé séparant ces régions de source et de drain. Une portion de la couche intermédiaire est placée sous une électrode de grille mais en est séparée par une couche isolante. Quand une polarisation convenable est appliquée à l'électrode de grille, le type de conductivité de la portion de couche intermédiaire placée sous cette grille s'inverse. Il y a alors continuité de type de conductivité entre la source et le drain et, si une différence de potentiel appropriée est appliquée entre source et drain, un courant peut circuler de l'un à l'autre. An insulated gate diffused field effect transistor (DMOS) is a semiconductor device with three electrodes essentially comprising source or drain regions or layers of the same type of conductivity and an intermediate region of the opposite conductivity type separating these source regions. and drain. A portion of the intermediate layer is placed under a gate electrode but is separated from it by an insulating layer. When a suitable polarization is applied to the grid electrode, the type of conductivity of the portion of intermediate layer placed under this grid is reversed. There is then continuity of type of conductivity between the source and the drain and, if an appropriate potential difference is applied between source and drain, a current can flow from one to the other.
On va exposer ci-après en relation avec les figures 1 et 2, illustrant des transistors à effet de champ de l'art antérieur dans lesquels la couche intermédiaire est obtenue par diffusion, la façon dont l'existence d'un transistor bipolaire parasite nuit au bon fonctionnement de tels transistors à effet de champ. We will explain below in relation to FIGS. 1 and 2, illustrating prior art field effect transistors in which the intermediate layer is obtained by diffusion, the way in which the existence of a parasitic bipolar transistor harms the proper functioning of such field effect transistors.
La figure 1 représente un transistor de type MOS à canal latéral diffusé classique, couramment appelé transistor
DMOS. Un tel transistor comprend un substrat 11 de type N+.FIG. 1 represents a MOS type transistor with conventional diffused side channel, commonly called transistor
DMOS. Such a transistor comprises an N + type substrate 11.
Sur ce substrat est formé par épitaxie une couche 12 de type N dans laquelle se trouvent deux régions diffusées de type N+13 et 14. La couche 13 est emboîtée dans une couche diffusée 15 de type P. Sur la surface supérieure de la couche 14 ou couche de drain est déposée une métallisation de drain D. Sur la surface supérieure de la couche 13 ou couche de source est déposée une métallisation de source S. La région 15 de type P dans laquelle est insérée la région de source 13 sera appelée région ou couche intermédiaire. Au-dessus d'une partie 17 de la région intermédiaire 15 est déposée une métallisation de grille G.On this substrate is formed by epitaxy an N-type layer 12 in which there are two diffused regions of type N + 13 and 14. The layer 13 is nested in a diffused layer 15 of type P. On the upper surface of the layer 14 or drain layer is deposited a drain metallization D. On the upper surface of the layer 13 or source layer is deposited a source metallization S. The region 15 of type P in which is inserted the source region 13 will be called region or intermediate layer. Above part 17 of the intermediate region 15 is deposited a gate metallization G.
Cette métallisation est isolée de la plaquette semiconductrice sous-jacente par une couche d'isolement 16, généralement une couche de silice. Ainsi, quand une polarisation est appliquée à la grille, il se forme dans la partie 17 de la couche intermédiaire sous-jacente une zone de canal à type de conductivité inversé par rapport à la conductivité initiale de la couche 15 et il n'existe donc plus de jonction bloquante entre les électrodes de source et de drain.This metallization is isolated from the underlying semiconductor wafer by an insulation layer 16, generally a layer of silica. Thus, when a polarization is applied to the grid, there is formed in the part 17 of the underlying intermediate layer a channel zone with a type of inverted conductivity with respect to the initial conductivity of the layer 15 and there therefore exists no more blocking junction between the source and drain electrodes.
On notera tout particulièrement dans la figure 1 que la métallisation de source S est en contact à la fois avec la partie supérieure de la couche de la source 13 et avec une partie supérieure de la couche intermédiaire 15, dans une région de cette couche éloignée de la zone de canal 17. Ce contact entre la métallisation de source et la couche intermédiaire 15 est destiné à assurer une polarisation facilitant le fonctionnement du transistor à effet de champ. It will be noted in particular in FIG. 1 that the source metallization S is in contact both with the upper part of the layer of the source 13 and with an upper part of the intermediate layer 15, in a region of this layer remote from the channel zone 17. This contact between the source metallization and the intermediate layer 15 is intended to ensure polarization facilitating the operation of the field effect transistor.
La figure 2 représente une autre configuration de transistor à effet de champ diffusé, connue usuellement sous l'appelation VMOS . Dans cette figure, les couches et zones ayant même fonction que les couches correspondantes de la figure 1 sont désignées par des nombres de référence dont le chiffre des unités est identique mais dont le chiffre des dizaines est de 2 au lieu d'être 1. Cette structure ne sera pas décrite en détail étant donné qu'elle est actuellement bien connue. Le drain est connecté à la face inférieure de la pastille désignée par la double référence 21-24 et le canal 27 se forme dans la partie de la couche intermédiaire 25 voisine d'une vallée ou tranchée 20 formée à partir de la face supérieure et dont l'arête se trouve dans la couche 22 de la façon représentée.On notera à nouveau dans cette figure que la métallisation de source S recouvre à la fois la couche de source 23 et une partie de la couche intermédiaire 25 dans une région éloignée de la zone de canal 27. FIG. 2 represents another configuration of a scattered field effect transistor, commonly known by the name VMOS. In this figure, the layers and zones having the same function as the corresponding layers in FIG. 1 are designated by reference numbers whose number of units is identical but whose tens figure is 2 instead of 1. This structure will not be described in detail since it is currently well known. The drain is connected to the lower face of the pellet designated by the double reference 21-24 and the channel 27 is formed in the part of the intermediate layer 25 adjacent to a valley or trench 20 formed from the upper face and whose the edge is in the layer 22 as shown. Note again in this figure that the source metallization S covers both the source layer 23 and part of the intermediate layer 25 in a region remote from the channel area 27.
Ense référant maintenant de façon générale aux figures 1 et 2, on notera que le dopage des couches de source 13 et 23 est généralement choisi à une valeur élevée de l'ordre de 1018 à 1020 at/cm3 et qu'ensuite, le dopage de la couche intermédiaire 15 est choisi pour que, dans la région de canal 17, on puisse obtenir la conduction du transistor MOS pour un seuil déterminé. Par exemple si, comme celà est usuel, on souhaite obtenir une tension de seuil relativement faible, de l'ordre du volt, il faudra choisir un dopage de l'ordre de 1016 à 1017 atomes/cm3 pour la couche intermédiaire 15. D'autre part, en ce qui concerne les structures des figures 1 et 2, les couches de source, intermédiaire, et de drain, forment également un transistor bipolaire parasite. Referring now generally to FIGS. 1 and 2, it will be noted that the doping of the source layers 13 and 23 is generally chosen at a high value of the order of 1018 to 1020 at / cm 3 and that, subsequently, the doping of the intermediate layer 15 is chosen so that, in the channel region 17, it is possible to obtain the conduction of the MOS transistor for a determined threshold. For example if, as is usual, one wishes to obtain a relatively low threshold voltage, of the order of a volt, it will be necessary to choose a doping of the order of 1016 to 1017 atoms / cm3 for the intermediate layer 15. D ' on the other hand, with regard to the structures of FIGS. 1 and 2, the source, intermediate and drain layers also form a parasitic bipolar transistor.
Une fois que le claquage drain-source du transistor à effet de champ est amorcé, étant donné que la métallisation de source est connectée à une partie de la couche intermédiaire éloignée de la zone du canal, il se produit une conduction à l'intérieur de la couche intermédiaire à partir de cette métallisation. La couche intermédiaire 25 ayant un niveau de dopage relativement faible et donc une résistivité relativement élevée, cette circulation de courant correspond à une variation de potentiel non négligeable par rapport à la chute de potentiel qui se produit par circulation de courant à l'intérieur de la couche de source-qui est, elle, à niveau de dopage très élevé et donc à faible résistivité. Ainsi, il pourra se produire une polarisation de la base (15, 25) du transistor bipolaire parasite par rapport à l'émetteur (13, 23) de ce transistor bipolaire parasite.Si le niveau de polarisation atteint sensiblement 0,7 volt, il se produira une conduction de la jonction émetteur-base de ce transistor bipolaire parasite et le transistor bipolaire parasite s'amorcera et provoquera une augmentation brutale du courant entre ses couches d'émetteur (13, 23) et de collecteur (14, 24? qui correspondent aux couches de source et de drain du transistor à effet de champ. Il en résulte un mauvais fonctionnement du transistor à effet de champ et même éventuellement une destruction du composant.Once the drain-source breakdown of the field effect transistor is initiated, since the source metallization is connected to a part of the intermediate layer remote from the zone of the channel, conduction occurs inside the intermediate layer from this metallization. Since the intermediate layer 25 has a relatively low doping level and therefore a relatively high resistivity, this current flow corresponds to a non-negligible variation in potential with respect to the drop in potential which occurs by current flow inside the source layer, which is very high doping level and therefore has low resistivity. Thus, there may be a polarization of the base (15, 25) of the parasitic bipolar transistor with respect to the emitter (13, 23) of this parasitic bipolar transistor. If the level of polarization reaches substantially 0.7 volts, it a conduction of the emitter-base junction of this parasitic bipolar transistor will occur and the parasitic bipolar transistor will start and will cause a sudden increase in the current between its layers of emitter (13, 23) and of collector (14, 24? which correspond to the source and drain layers of the field effect transistor, resulting in a malfunction of the field effect transistor and even possibly destruction of the component.
Un objet de la présente invention est de prévoir un transistor à effet de champ dans lequel l'influence du transistor bipolaire parasite est minimisée. An object of the present invention is to provide a field effect transistor in which the influence of the parasitic bipolar transistor is minimized.
Un autre objet de la présente invention est de prévoir un tel transistor à effet de champ dont la tension de seuil est ajustable. Another object of the present invention is to provide such a field effect transistor whose threshold voltage is adjustable.
Pour atteindre ces objets ainsi que d'autres, la présente invention prévoit un transistor à effet de champ comprenant des couches de drain et de source du même type de conductivité et une couche intermédiaire du type de conductivité opposé dans une partie de laquelle peut se former, par suite de la polarisation de la grille et en-dessous de celle-ci, une zone de canal, dans lequel le niveau de dopage de la zone de canal est plus faible que celui du reste de la couche intermédiaire. Ainsi, le dopage de la couche intermédiaire peut être choisi à une valeur suffisamment élevée pour que sa résistivite soit suffisamment faible pour éviter le déclenchement du transistor bipolaire parasite alors que le dopage de la région de canal de cette couche intermédiaire est choisi pour déterminer le seuil désiré de déclenchement du transistor MOS. To achieve these and other objects, the present invention provides a field effect transistor comprising drain and source layers of the same type of conductivity and an intermediate layer of the opposite type of conductivity in a part of which may form. , as a result of the polarization of the gate and below it, a channel zone, in which the doping level of the channel zone is lower than that of the rest of the intermediate layer. Thus, the doping of the intermediate layer can be chosen at a sufficiently high value so that its resistivity is sufficiently low to avoid tripping of the parasitic bipolar transistor while the doping of the channel region of this intermediate layer is chosen to determine the threshold. desired triggering of the MOS transistor.
De préférence la couche intermédiaire est formée par diffusion et la modification du niveau de conductivité du canal est déterminée par une implantation d'impuretés du type de conductivité opposé à celles initialement diffuséesdans la couche intermédiaire. Ainsi, pour la couche intermédiaire, on pourra 18 3 choisir un dopage de l'ordre de 1017 à 1018 atomes/cm alors que ce dopage sera ramené à une valeur de l'ordre de 1016 à 1017 atomes/cm3 dans la région de canal. Preferably the intermediate layer is formed by diffusion and the change in the conductivity level of the channel is determined by implantation of impurities of the conductivity type opposite to those initially diffused in the intermediate layer. Thus, for the intermediate layer, it will be possible to choose a doping of the order of 1017 to 1018 atoms / cm while this doping will be reduced to a value of the order of 1016 to 1017 atoms / cm3 in the channel region. .
Ces objets, caractéristiques et avantages ainsi que d'autres de la présente invention seront exposés plus en détail dans la description suivante de modes de réalisation particuliers faite en relation avec les figures jointes parmi lesquelles
- la figure 1 représente un transistor de type DMOS de l'art antérieur
- la figure 2 représente un transistor de type VMOS de l'art antérieur ;
- la figure 3 représente un transistor de type DMOS selon la présente invention ; et
- la figure 4 représente un transistor VMOS selon la présente invention.These objects, characteristics and advantages as well as others of the present invention will be explained in more detail in the following description of particular embodiments made in relation to the attached figures among which
- Figure 1 shows a DMOS transistor of the prior art
- Figure 2 shows a VMOS transistor of the prior art;
- Figure 3 shows a DMOS type transistor according to the present invention; and
- Figure 4 shows a VMOS transistor according to the present invention.
De façon générale, on notera que ces figures sont fortement schématiques et que, notamment en ce qui concerne l'épaisseur et les dimensions des diverses couches, elles ne correspondent pas à un tracé à l'échelle. Elles sont uniquement destinées à illustrer la présente invention. Notamment, la région de canal a été représentée élargie en figure 3 par rapport à la figure 1, ceci est uniquement destiné à mieux représenter la zone dans laquelle se situent les modifications de caractéristiques effectuées selon l'invention. In general, it will be noted that these figures are highly schematic and that, in particular as regards the thickness and the dimensions of the various layers, they do not correspond to a layout to scale. They are only intended to illustrate the present invention. In particular, the channel region has been shown enlarged in FIG. 3 compared with FIG. 1, this is only intended to better represent the zone in which the modifications of characteristics carried out according to the invention are situated.
La figure 3 représente un transistor à effet de champ de type Dr4os dans lequel de mêmes références désignent des éléments et des couches analogues à ceux désignés de façon identique en figure 1. On notera que la figure 3 comprend une zone 18, recouvrant notamment la zone de canal 17, dans laquelle on a procédé à une implantation d'ions. Le niveau de dopage de la couche intermédiaire 15 est choisi à une 17 16 3 valeur plus élevée, par exemple de 10 à 10 atomes/cm3, que dans le cas de la figure 1 où ce niveau de dopage était de l'ordre de 1016 a 1017 atomes/cm3.Ainsi, la circulation de courant dans la couche intermédiaire 15 à partir de la métallisation S vers la zone de canal qui a maintenant lieu dans une zone moins résistive entraînera une plus faible chute de tension par rapport à la couche de la source 13. Le transistor bipolaire parasite vertical sera donc peu susceptible d'être amorcé.L'implantation ionique 18 est effectuée à partir d'ions fournissant un type de conductivité N, c'est-àdire que le dopage résultant dans la zone 17 restera de type
P mais à plus faible niveau de dopage, par exemple de l'ordre de 1016 à 1017 atomes/cm3, ce niveau étant choisi pour optimiser le seuil d'ouverture de canal du transistor DM08. Bien que celà ne soit pas représenté dans la figure, on notera que l'étendue de la zone implantée 18 peut correspondre sensiblement à celle de la grille, c'est-à-dire que, lors des étapes de fabrication du composant, on pourra se servir des ouvertures ménagées pour former la grille pour servir de masque d'implantation.FIG. 3 represents a field effect transistor of the Dr4os type in which the same references designate elements and layers similar to those designated identically in FIG. 1. It will be noted that FIG. 3 comprises an area 18, covering in particular the area of channel 17, in which an ion implantation was carried out. The doping level of the intermediate layer 15 is chosen to have a higher value, for example from 10 to 10 atoms / cm 3, than in the case of FIG. 1 where this doping level was of the order of 1016 has 1017 atoms / cm3. Thus, the current flow in the intermediate layer 15 from the metallization S towards the channel zone which now takes place in a less resistive zone will cause a lower voltage drop compared to the layer of the source 13. The vertical parasitic bipolar transistor will therefore be unlikely to be primed. The ion implantation 18 is carried out using ions providing a type of conductivity N, that is to say that the resulting doping in the area 17 will remain of type
P but at a lower doping level, for example of the order of 1016 to 1017 atoms / cm3, this level being chosen to optimize the channel opening threshold of the transistor DM08. Although this is not shown in the figure, it will be noted that the extent of the implanted area 18 can correspond substantially to that of the grid, that is to say that, during the steps of manufacturing the component, it will be possible to use the openings made to form the grid to serve as an implantation mask.
La figure 4 représente un transistor de type VMOS analogue à celui de la figure 2, dans lequel de mêmes références désignent des éléments et couches identiques à ceux désignés de la même façon en figure 2. On notera l'implantation ionique 28 réalisée notamment dans les zones de canal 27 de la couche intermédiaire 25. De la même façon que dans le cas de la figure 3 celà permet de choisir le niveau de dopage de l'ensemble de la couche intermédiaire 25 pour minimiser l'influence du transistor bipolaire vertical, tout en optimisant le niveau de dopage dans la zone de canal 27 de cette couche intermédiaire. On peut donc ajuster la tension de seuil du transistor à effet de champ sans être géné par les contraintes imposées par le transistor bipolaire parasite. FIG. 4 represents a VMOS type transistor analogous to that of FIG. 2, in which the same references designate elements and layers identical to those designated in the same way in FIG. 2. Note the ion implantation 28 carried out in particular in channel zones 27 of the intermediate layer 25. In the same way as in the case of FIG. 3, this makes it possible to choose the doping level of the assembly of the intermediate layer 25 to minimize the influence of the vertical bipolar transistor, while by optimizing the doping level in the channel region 27 of this intermediate layer. It is therefore possible to adjust the threshold voltage of the field effect transistor without being hampered by the constraints imposed by the parasitic bipolar transistor.
On a décrit précédemment des transistors MOS dans lesquels le drain et la source étaient de type N, c'est-àdire des transistors MOS à canal N. Bien entendu tous les types de conductivité peuvent être inversés pour former des transistors MOS à canal P. MOS transistors have previously been described in which the drain and the source are of type N, that is to say N channel MOS transistors. Of course, all types of conductivity can be reversed to form P channel MOS transistors.
En outre, on a donné des exemples de transistors MOS de type à eprichissement, c'est-à-dire dans lesquels le canal est non conducteur en l'absence de polarisation de grille. La présente invention s'applique également à des transistors MOS du type à appauvrissement, c'est-à-dire dans lesquels la zone de canal est conductrice en l'absence de champ appliqué sur la grille et devient non conductrice quand on applique une polarisation de grille. In addition, examples have been given of MOS transistors of the eprichissement type, that is to say in which the channel is non-conductive in the absence of gate polarization. The present invention also applies to MOS transistors of the depletion type, that is to say in which the channel zone is conductive in the absence of a field applied to the grid and becomes non-conductive when a polarization is applied. grid.
Le transistor à effet de champ selon la présente invention peut être utilisé comme composant discret ou bien faire partie d'un circuit intégré monolithique. The field effect transistor according to the present invention can be used as a discrete component or else be part of a monolithic integrated circuit.
La présente invention n'est pas limitée aux modes de réalisation explicitement décrits mais en engloge les diverses variantes et généralisations contenues dans les revendications ci-après. The present invention is not limited to the embodiments explicitly described but encompasses the various variants and generalizations contained in the claims below.
Dans les revendications ci-apres, on entend par "couche de drain" l'ensemble des couches de même type de con ductivité reliées à la métallisatioii de drain, c'est à dire les couches 12 et 14 des figures 1 et 3 et les couches 22 et 24 des figures 2 et 4. In the claims below, the term "drain layer" means all the layers of the same type of conductivity connected to the drain metallization, that is to say the layers 12 and 14 of FIGS. 1 and 3 and the layers 22 and 24 of Figures 2 and 4.
Claims (5)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR7914991A FR2458907A1 (en) | 1979-06-12 | 1979-06-12 | Field effect transistor with adjustable pinch off voltage - has doping chosen in intermediate layer to reduce effect of parasitic bipolar transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR7914991A FR2458907A1 (en) | 1979-06-12 | 1979-06-12 | Field effect transistor with adjustable pinch off voltage - has doping chosen in intermediate layer to reduce effect of parasitic bipolar transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| FR2458907A1 true FR2458907A1 (en) | 1981-01-02 |
| FR2458907B1 FR2458907B1 (en) | 1982-11-26 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| FR7914991A Granted FR2458907A1 (en) | 1979-06-12 | 1979-06-12 | Field effect transistor with adjustable pinch off voltage - has doping chosen in intermediate layer to reduce effect of parasitic bipolar transistor |
Country Status (1)
| Country | Link |
|---|---|
| FR (1) | FR2458907A1 (en) |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2487583A1 (en) * | 1980-07-25 | 1982-01-29 | Thomson Csf | Groove FET mfr. - with intermediate oxidn. in steam and oxide removal to control dopant concn. locally |
| EP0066081A2 (en) * | 1981-05-22 | 1982-12-08 | International Business Machines Corporation | Dense vertical FET and method of making |
| FR2511194A1 (en) * | 1981-08-04 | 1983-02-11 | Siliconix Inc | FIELD EFFECT TRANSISTOR AND METHOD OF MANUFACTURE |
| EP0081269A2 (en) * | 1981-12-07 | 1983-06-15 | Philips Electronics Uk Limited | Insulated-gate field-effect transistors |
| FR2518816A1 (en) * | 1981-12-18 | 1983-06-24 | Nissan Motor | METAL-OXIDE-SEMICONDUCTOR FIELD EFFECT TRANSISTOR |
| EP0114435A1 (en) * | 1982-12-21 | 1984-08-01 | Koninklijke Philips Electronics N.V. | Lateral DMOS transistor devices suitable for sourcefollower applications |
| EP0115098A1 (en) * | 1982-12-27 | 1984-08-08 | Koninklijke Philips Electronics N.V. | Lateral DMOS transistor device having an injector region |
| EP0407011A2 (en) * | 1989-07-03 | 1991-01-09 | Harris Corporation | Insulated gate semiconductor devices |
| CN105336785A (en) * | 2014-08-15 | 2016-02-17 | 北大方正集团有限公司 | Depletion-type VDMOS device and manufacturing method therefor |
| CN105448733A (en) * | 2014-09-02 | 2016-03-30 | 北大方正集团有限公司 | Depletion type VDMOS device and manufacturing method thereof |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105990399A (en) * | 2015-01-27 | 2016-10-05 | 北大方正集团有限公司 | Method and device for manufacturing depletion type MOSFET |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE2136509A1 (en) * | 1970-07-24 | 1972-11-23 | Hitachi Ltd., Tokio | Semiconductor device |
| GB1328874A (en) * | 1969-09-30 | 1973-09-05 | Sprague Electric Co | Semiconductor devices |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1328874A (en) * | 1969-09-30 | 1973-09-05 | Sprague Electric Co | Semiconductor devices |
| DE2136509A1 (en) * | 1970-07-24 | 1972-11-23 | Hitachi Ltd., Tokio | Semiconductor device |
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Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2487583A1 (en) * | 1980-07-25 | 1982-01-29 | Thomson Csf | Groove FET mfr. - with intermediate oxidn. in steam and oxide removal to control dopant concn. locally |
| EP0066081A2 (en) * | 1981-05-22 | 1982-12-08 | International Business Machines Corporation | Dense vertical FET and method of making |
| EP0066081A3 (en) * | 1981-05-22 | 1985-09-11 | International Business Machines Corporation | Dense vertical fet and method of making |
| FR2511194A1 (en) * | 1981-08-04 | 1983-02-11 | Siliconix Inc | FIELD EFFECT TRANSISTOR AND METHOD OF MANUFACTURE |
| EP0081269A3 (en) * | 1981-12-07 | 1984-12-27 | Philips Electronic And Associated Industries Limited | Insulated-gate field-effect transistors |
| EP0081269A2 (en) * | 1981-12-07 | 1983-06-15 | Philips Electronics Uk Limited | Insulated-gate field-effect transistors |
| US4697201A (en) * | 1981-12-18 | 1987-09-29 | Nissan Motor Company, Limited | Power MOS FET with decreased resistance in the conducting state |
| FR2518816A1 (en) * | 1981-12-18 | 1983-06-24 | Nissan Motor | METAL-OXIDE-SEMICONDUCTOR FIELD EFFECT TRANSISTOR |
| EP0114435A1 (en) * | 1982-12-21 | 1984-08-01 | Koninklijke Philips Electronics N.V. | Lateral DMOS transistor devices suitable for sourcefollower applications |
| EP0115098A1 (en) * | 1982-12-27 | 1984-08-08 | Koninklijke Philips Electronics N.V. | Lateral DMOS transistor device having an injector region |
| EP0407011A2 (en) * | 1989-07-03 | 1991-01-09 | Harris Corporation | Insulated gate semiconductor devices |
| EP0407011A3 (en) * | 1989-07-03 | 1991-03-13 | Harris Corporation | Insulated gate semiconductor devices |
| CN105336785A (en) * | 2014-08-15 | 2016-02-17 | 北大方正集团有限公司 | Depletion-type VDMOS device and manufacturing method therefor |
| CN105336785B (en) * | 2014-08-15 | 2019-03-29 | 北大方正集团有限公司 | A kind of depletion type VDMOS device and preparation method thereof |
| CN105448733A (en) * | 2014-09-02 | 2016-03-30 | 北大方正集团有限公司 | Depletion type VDMOS device and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| FR2458907B1 (en) | 1982-11-26 |
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