FR2488046A1 - DMOS controlled semiconductor power device - uses DMOS FET to drive thyristor with photodiodes deposited on insulating layer with power device using most of substrate area - Google Patents
DMOS controlled semiconductor power device - uses DMOS FET to drive thyristor with photodiodes deposited on insulating layer with power device using most of substrate area Download PDFInfo
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- 239000000758 substrate Substances 0.000 title claims abstract description 18
- 239000004065 semiconductor Substances 0.000 title claims description 10
- 230000005669 field effect Effects 0.000 claims abstract description 23
- 238000001465 metallisation Methods 0.000 claims abstract description 13
- 238000009792 diffusion process Methods 0.000 claims abstract description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 5
- 230000003287 optical effect Effects 0.000 claims abstract description 4
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- 101000993469 Homo sapiens Beta-catenin-interacting protein 1 Proteins 0.000 claims 1
- 150000002500 ions Chemical class 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052710 silicon Inorganic materials 0.000 abstract description 2
- 239000010703 silicon Substances 0.000 abstract description 2
- 229920005591 polysilicon Polymers 0.000 abstract 1
- 238000000034 method Methods 0.000 description 3
- 241001354791 Baliga Species 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000003321 amplification Effects 0.000 description 2
- 238000003199 nucleic acid amplification method Methods 0.000 description 2
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- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000284 resting effect Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/1443—Devices controlled by radiation with at least one potential jump or surface barrier
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
- H01L27/0705—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/7302—Bipolar junction transistors structurally associated with other devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
- H01L29/749—Thyristor-type devices, e.g. having four-zone regenerative action with turn-on by field effect
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
- H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by at least one potential-jump barrier or surface barrier, e.g. phototransistors
- H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
- H01L31/112—Devices sensitive to infrared, visible or ultraviolet radiation characterised by field-effect operation, e.g. junction field-effect phototransistor
- H01L31/113—Devices sensitive to infrared, visible or ultraviolet radiation characterised by field-effect operation, e.g. junction field-effect phototransistor being of the conductor-insulator-semiconductor type, e.g. metal-insulator-semiconductor field-effect transistor
- H01L31/1136—Devices sensitive to infrared, visible or ultraviolet radiation characterised by field-effect operation, e.g. junction field-effect phototransistor being of the conductor-insulator-semiconductor type, e.g. metal-insulator-semiconductor field-effect transistor the device being a metal-insulator-semiconductor field-effect transistor
Abstract
Description
La présente invention concerne une structure semiconductrice intégrée associant un dispositif de puissance et un dispositif de commande du type transistor a effet de champ a grille isolée. Elle s'applique plus particulièrement aux thyristors et transistors de puissance. The present invention relates to an integrated semiconductor structure associating a power device and a control device of the insulated gate field effect transistor type. It applies more particularly to thyristors and power transistors.
Il est connu depuis longtemps d'associer sous forme intégrée a des transistors ou des thyristors de puissance des composants de déclenchement du type bipolaire. On obtient ainsi pour les transistors des dispositifs du type Darlington et pour les thyristors des dispositifs du type thyristor a amplification de gachette. It has long been known to combine, in integrated form with power transistors or thyristors, trip components of the bipolar type. There are thus obtained for the transistors devices of the Darlington type and for the thyristors of the devices of the thyristor type with gate amplification.
Ces dernières années, à la suite de l'amélioration de la tenue en tension des composants à effet de champ, on a développé des structures intégrées permettant la commande de composants semiconducteurs de puissance par des dispositifs du type a effet de champ. Une telle structure est par exemple décrite dans l'article de
B.J. Baliga paru dans Electronics Letters le 27 septembre 1979, pages 645 a 647. Dans cet article, Baliga rappelle les avantages essentiels des thyristors a commande par transistor a effet de champ, qui sont notamment d'une part de réduire la puissance de commande nécessaire au déclenchement, d'autre part de permettre une commande indépendante de la sensibilité de gâchette et de la tenue en dV/dt du dispositif.Le dispositif particulier décrit par Baliga est un thyristor associé a un transistor a effet de champ du type VMOS, c'est- -dire un transistor à effet de champ à grille isolée a rainures en V et a fonctionnement vertical. Un inconvénient notable d'un tel dispositif reside dans la nécessité de prévoir toute une structure maillée de rainures en V à sa surface ; il en résulte une occupation de surface importante pour le système de déclenchement par rapport à la surface de cathode, ce qui, pour une puissance donnée exige d'aug menter la taille de la pastille semiconductrice, et accroît les risques de mauvais rendement de fabrication.In recent years, following the improvement of the voltage withstand of field effect components, integrated structures have been developed allowing the control of power semiconductor components by devices of the field effect type. Such a structure is for example described in the article by
BJ Baliga appeared in Electronics Letters on September 27, 1979, pages 645 to 647. In this article, Baliga recalls the essential advantages of thyristors with field effect transistor control, which are notably on the one hand to reduce the necessary control power on triggering, on the other hand to allow independent control of the trigger sensitivity and of the device's dV / dt resistance. The particular device described by Baliga is a thyristor associated with a field effect transistor of the VMOS type, c is an insulated gate field effect transistor with V grooves and vertical operation. A notable drawback of such a device lies in the need to provide an entire mesh structure of V-grooves on its surface; this results in a large surface occupation for the trigger system relative to the cathode surface, which, for a given power requires increasing the size of the semiconductor wafer, and increases the risk of poor manufacturing efficiency.
Ainsi, un objet de la présente invention est de prévoir une nouvelle structure de composant de puissance à commande par transistor à eftet de champ qui permette un particulièrement bon rendement de fabrication. Thus, an object of the present invention is to provide a new power component structure controlled by a field effect transistor which allows a particularly good manufacturing efficiency.
Un autre objet de la présente invention est de prévoir une telle structure dans laquelle le déclenchement peut être'commandé optiquement. Another object of the present invention is to provide such a structure in which the trigger can be optically controlled.
Pour atteindre ces objets ainsi que d'autres, la présente invention prévoit que le transistor à effet de champ de déclenchement est du type DMOS à fonctionnement vertical (l'abréviation DMOS désigne un transistor à effet de champ à grille isolée obtenue par double diffusion et cette appellation sera utilisée ci-apres par souci de brièveté,
Le dispositif de puissance comprend un substrat d'un premier type de conductivité à faible niveau de dopage, revêtu sur une première face d'une couche de commande du deuxième type de conductivité, elle-même revêtue d'une couche principale du premier type de con ductivité. La couche de commande et la couche principale occupent la plus grande partie de la première face.To achieve these and other objects, the present invention provides that the trigger field effect transistor is of the DMOS type with vertical operation (the abbreviation DMOS designates an isolated gate field effect transistor obtained by double diffusion and this designation will be used below for the sake of brevity,
The power device comprises a substrate of a first type of conductivity at low doping level, coated on a first face with a control layer of the second type of conductivity, itself coated with a main layer of the first type of conductivity. The control layer and the main layer occupy most of the first face.
La partie restée libre porte la structure DMOS dont le drain correspond au substrat et dont la couche intermédiaire de même type de conductivité que la couche de commande est continue avec c-elle-ci mais à plus faible niveau de dopage. La grille du DMOS est de préférence en silicium polycristallin.The part which remains free carries the DMOS structure, the drain of which corresponds to the substrate and the intermediate layer of the same type of conductivity as the control layer is continuous therewith but at a lower doping level. The DMOS grid is preferably made of polycrystalline silicon.
Pour obtenir une structure à déclenchement optique, la présente invention prévoit de disposer plusieurs diodes polycristallines sur une couche isolante déposée sur la première face, ces diodes étant connectées en série par des métallisations et les bornes extrêmes de ce montage série étant connectées respectivement à la couche de commande et à la grille du DMOS. Le dispositif de puissance peut être un thyristor, alors la deuxieme face du substrat est recouverte d'une couche du deuxième type de conductivité. Ce peut également etre un transistor, alors la deuxième face du substrat est recouverte dune couche du premier type de conductivité à haut niveau de dopage. To obtain an optically triggered structure, the present invention provides for having several polycrystalline diodes on an insulating layer deposited on the first face, these diodes being connected in series by metallizations and the extreme terminals of this series arrangement being connected respectively to the layer and the DMOS grid. The power device can be a thyristor, then the second face of the substrate is covered with a layer of the second type of conductivity. It can also be a transistor, so the second face of the substrate is covered with a layer of the first type of conductivity with a high level of doping.
Ces objets, caractéristiques et avantages ainsi que d'autres de la présente invention seront exposés plus en détail dans la description suivante de modes de réalisation particuliers faite en relation avec les figures jointes parmi lesquelles
la figure 1 rappelle le schéma électrique équivalent de l'association d'un transistor à effet de champ et d'un thyristor
la figure 2 représente une vue en coupe schématique d'une structure intégrée selon la présente invention
la figure 3 représente une vue de dessus schématique d'une structure selon la présente invention (sans les couches de métallisation).These objects, characteristics and advantages as well as others of the present invention will be explained in more detail in the following description of particular embodiments made in relation to the attached figures among which
Figure 1 recalls the equivalent electrical diagram of the association of a field effect transistor and a thyristor
2 shows a schematic sectional view of an integrated structure according to the present invention
FIG. 3 represents a schematic top view of a structure according to the present invention (without the metallization layers).
Conformément à l'usage dans la représentation des dispositifs semiconducteurs, aucune des deux figures 2 et 3 n'est tracée à l'échelle en ce qui concerne la profondeur ou les dimensions relatives des diverses couches. In accordance with the practice in the representation of semiconductor devices, neither of the two figures 2 and 3 is drawn to scale with regard to the depth or the relative dimensions of the various layers.
Ces figures sont seulement illustratives et ont pour but de faire comprendre la présente invention. Pour les dimensions des diverses structures, on se référera aux connaissances habituelles dans la technique de la fabrication des semiconducteurs sauf indications particulières données dans le texte ci après.These figures are only illustrative and are intended to explain the present invention. For the dimensions of the various structures, reference is made to the usual knowledge in the technique of manufacturing semiconductors, unless otherwise indicated in the text below.
La figure 1 représente l'association d'un thyristor 1 et d'un dispositif de commande à effet de champ 2. FIG. 1 represents the association of a thyristor 1 and a field effect control device 2.
Ce dispositif comprend deux bornes principales 3 et 4 entre lesquelles est appliqué le courant à interrompre et une borne de commande 5 référencée a la borne 4. La source du transistor à effet de champ 2 est connectée à l'anode du thyristor 1, son drain est connecté à la gâchette du thyristor et sa grille à la borne de commande 5. On a également représente en figure 1 une série de diodes photosensibles 6 qui peuvent servir à assurer une commande optique du thyristor par l'intermédiaire du transistor à effet de champ. On soulignera cette application particulière qui n'est pas concevable dans le cas où le thyristor est commandé par un autre thyristor car alors les courants de commande seraient trop importants pour permettre une commande optique.This device comprises two main terminals 3 and 4 between which the current to be interrupted is applied and a control terminal 5 referenced to terminal 4. The source of the field effect transistor 2 is connected to the anode of the thyristor 1, its drain is connected to the trigger of the thyristor and its gate to the control terminal 5. FIG. 1 also shows a series of photosensitive diodes 6 which can be used to provide optical control of the thyristor by means of the field effect transistor . We will emphasize this particular application which is not conceivable in the case where the thyristor is controlled by another thyristor because then the control currents would be too large to allow an optical control.
La présente invention vise des modes de réalisation particuliers du montage de la figure 1, également dans le cas où le thyristor 1 est remplacé par un transistor, les bornes d'anode, de cathode et de gâchette étant alors respectivement les bornes d'émetteur, de collecteur et de base. Quand on voudra désigner de façon générale les bornes dlun thyristor ou d'un transistor, on parlera de bornes principales pour désigner les bornes d'anode ou d'émetteur d'une part et de cathode ou de collecteur d'autre part et de borne de commande pour désigner la borne de gâchette ou de base. The present invention relates to particular embodiments of the assembly of FIG. 1, also in the case where the thyristor 1 is replaced by a transistor, the anode, cathode and trigger terminals then being respectively the emitter terminals, manifold and base. When we want to generally designate the terminals of a thyristor or a transistor, we will speak of main terminals to designate the anode or emitter terminals on the one hand and the cathode or collector on the other hand and the terminal to designate the trigger or base terminal.
Les figures 2 et 3 illustrent une vue en coupe schématique et une vue de dessus schématique d'une association d'un thyristor et d'un transistor à effet de champ du type DMOS selon la présente invention. On notera que la figure 2 ne correspond pas strictement à une vue en coupe de la figure 3 mais est en fait une coupe fonctionnelle destinée à mieux illustrer le fonctionnement de la présente invention De même, dans la figure 3, la zone de commande a été représentée comme occupant un coin d'un thyristor, dans la pratique, cette zone de commande pourra être disposée à tout autre endroit souhai- té, par exemple de façon centrale. Figures 2 and 3 illustrate a schematic sectional view and a schematic top view of a combination of a thyristor and a DMOS type field effect transistor according to the present invention. Note that Figure 2 does not strictly correspond to a sectional view of Figure 3 but is in fact a functional section intended to better illustrate the operation of the present invention Similarly, in Figure 3, the control area has been shown as occupying a corner of a thyristor, in practice, this control zone can be placed at any other desired location, for example centrally.
Comme le représente la figure 2, la structure selon la présente invention comprend un substrat semiconducteur 10, couramment du silicium, faiblement dopé de type N (désigné par N ). Sur la plus grande partie de la première face du substrat est formée une couche 11 de type P également désignée par P1. Cette couche de type P sera habituellement formée par diffusion, par exemple au bore. Dans la plus grande partie de la couche 11 est formée, couramment par diffusion, une couche 12 de type N, également désignée par la référence N1.On notera que, pour un thyristor, comme cela est représenté dans cette figure, cette couche 12 est interrompue pour permettre des remontées en surface de la couche P1, ce qui correspond à la structure couramment désignée par l'appel- lation court-circuit d'émetteur assurant un meilleur fonctionnement en dV/dt du thyristor. Une métallisation 13 recouvre la couche Ni et les remontées de la couche Pi et constitue la métallisation de cathode. La partie de déclenchement de la structure est du type transistor à effet de champ à double diffusion et comprend une couche 14, également désignée par la référence PO continue avec la couche Pi mais à plus faible niveau de dopage.A l'intérieur de cette couche PO et vers la frontière de cette couche PO avec la remontée en surface de la couche de substrat 10, est formée une zone diffusée 15 de type N également désignée par la référence NO. La couche PO sera appelée couche intermédiaire et la zone étroite de cette couche PO séparant'horizontalement la couche NO 15 de la couche N 10 constitue la zone de canal du transistor DMOS. Cette zone de canal est surmontée par une couche isolante, couramment de la silice 16 ellemême revêtue d'une couche conductrice de grille 17 permettant d'ouvrir ou de fermer le canal selon la tension appliquée.Dans le cas particulier représenté, la couche conductrice 17 est une couche de silicium polycristallin, des techniques bien connues pouvant être utilisées pour auto-aligner les frontières des couches PO et NO avec les projections de cette couche 17 pour permettre l'obtention de structure très bien définie par des techniques d'auto-alignement. La couche 15 constitue la source du transistor DMOS dont le substrat 10 constitue le drain, le contact avec ce substrat étant effectué par l'inter médiaire d'une couche 18 de type N+. En regard de la zone de cathode du thyristor est formée sur le substrat une couche 19 de type P+ correspondant à l'anode du thyristor. L'ensemble des couches N et P+ est revêtu d'une métallisation 20. As shown in Figure 2, the structure according to the present invention comprises a semiconductor substrate 10, commonly silicon, lightly doped N-type (designated by N). On the major part of the first face of the substrate is formed a layer 11 of type P also designated by P1. This P-type layer will usually be formed by diffusion, for example boron. In the major part of the layer 11 is formed, commonly by diffusion, a layer 12 of type N, also designated by the reference N. 1. It will be noted that, for a thyristor, as shown in this figure, this layer 12 is interrupted to allow the surface P1 to rise to the surface, which corresponds to the structure commonly designated by the term short-circuit emitter ensuring better operation in dV / dt of the thyristor. A metallization 13 covers the Ni layer and the rising of the Pi layer and constitutes the cathode metallization. The tripping part of the structure is of the double diffusion field effect transistor type and comprises a layer 14, also designated by the reference PO continuous with the layer Pi but at a lower doping level. Inside this layer PO and towards the border of this layer PO with the rise to the surface of the substrate layer 10, a diffused zone 15 of type N is also formed, designated by the reference NO. The PO layer will be called the intermediate layer and the narrow area of this PO layer horizontally separating the NO layer 15 from the N layer 10 constitutes the channel area of the DMOS transistor. This channel zone is surmounted by an insulating layer, usually silica 16 itself coated with a conductive grid layer 17 making it possible to open or close the channel according to the applied voltage. In the particular case shown, the conductive layer 17 is a polycrystalline silicon layer, well known techniques that can be used to self-align the boundaries of the PO and NO layers with the projections of this layer 17 to allow obtaining a structure very well defined by self-alignment techniques . Layer 15 constitutes the source of the DMOS transistor whose substrate 10 constitutes the drain, the contact with this substrate being effected by the intermediary of a layer 18 of N + type. Opposite the cathode zone of the thyristor is formed on the substrate a layer 19 of P + type corresponding to the anode of the thyristor. All of the layers N and P + are coated with a metallization 20.
La commande du dispositif selon la présente invention peut s'effectuer directement par application externe d'une tens-ion sur la couche conductrice 17. The device according to the present invention can be controlled directly by external application of a tension to the conductive layer 17.
Néanmoins, étant donné qu'un transistor MOS peut se commander avec de faibles courants, il est'envisagé selon la présente invention d'effectuer la commande de façon optique en formant sur la couche isolante 16 plusieurs diodes polycristallines constituées du même polycristal que celui qui est utilisé pour former la couche de grille 17, ces régions polycristallines, désignées par la référence 21, étant partagées en des régions dopées de type différent, ces dopages différents s'effectuant en même temps que les diffusions NO et PO à l'aide de masques appropriés. Des métallisations 22 sont prévues pour disposer les diodes en série et connecter la diode extrême par rapport à la grille à la couche P et assurer ainsi la polarisation de l'ensemble.However, since a MOS transistor can be controlled with low currents, it is envisaged according to the present invention to perform the control optically by forming on the insulating layer 16 several polycrystalline diodes made of the same polycrystal as that which is used to form the gate layer 17, these polycrystalline regions, designated by the reference 21, being divided into doped regions of different type, these different dopings taking place at the same time as the NO and PO diffusions using appropriate masks. Metallizations 22 are provided to arrange the diodes in series and connect the extreme diode relative to the grid to the layer P and thus ensure the polarization of the assembly.
On notera également à la surface supérieure du dispositif une métallisation 23 reposant sur des portions des surfaces des couches 14 et 15. Cette métallisation a le ralle classique de polarisation de la zone intermédiaire. Note also on the upper surface of the device a metallization 23 resting on portions of the surfaces of the layers 14 and 15. This metallization has the conventional shape of polarization of the intermediate zone.
La structure représentée est susceptible de nombreuses variantes. Notamment, à la face inférieure,on a représenté une couche 18 de type N sous la zone de commande. On obtient bien ainsi un transistor à effet de champ à double diffusion de type vertical classique. The structure shown is susceptible of numerous variants. In particular, on the underside, an N-type layer 18 has been represented under the control area. This produces a double-field field effect transistor of the conventional vertical type.
Néanmoins, cette couche 18 pourrait être le prolongement de la couche 19 de type P+ étant donné que la jonction entre les couches 10 et 19 se trouve polarisée dans le bon sens pour le déclenchement et ne constituerait pas une barrière.D'autre part, bien que le mode de réalisation des diodes photosensibles 21, sous forme de diodes polycristallines déposées à la surface du dispositif soit actuellement le mode de réalisation considéré comme préféré par les inventeurs, on notera que ces diodes pourraient être formées de zones N localisées disposées dans la région de la couche 11 non recouverte d'une métallisation, à savoir la région représentée à la partie supérieure gauche de la figure 2.Ceci est possible dans le cas particulier de la structure représentée car les diodes photosensibles se trouveraient alors polarisées de façon convenable, ce qui n'est habituellement pas le cas pour les dispositifs semiconducteurs intégrés.However, this layer 18 could be an extension of the P + type layer 19 since the junction between layers 10 and 19 is polarized in the right direction for triggering and would not constitute a barrier. that the embodiment of the photosensitive diodes 21, in the form of polycrystalline diodes deposited on the surface of the device is currently the embodiment considered to be preferred by the inventors, it will be noted that these diodes could be formed from localized N zones arranged in the region layer 11 not covered with a metallization, namely the region shown in the upper left-hand part of FIG. 2. This is possible in the particular case of the structure shown since the photosensitive diodes would then be suitably polarized, this which is not usually the case for integrated semiconductor devices.
La figure 3 représente à titre d'exemple une vue de dessus du dispositif de la figure 2 sans les diverses métallisations. Les zones correspondant à celles de la figure 2 sont désignées par de mêmes références. Les diverses diodes polycristallines 21 pourraient se trouver par exemple disposées le long des bords de la structure sur une couche isolante. Dans la zone de commande, la région délimitée par des pointillés correspond sensiblement à celle de la zone conductrice de grille 17. Figure 3 shows by way of example a top view of the device of Figure 2 without the various metallizations. The zones corresponding to those of FIG. 2 are designated by the same references. The various polycrystalline diodes 21 could for example be arranged along the edges of the structure on an insulating layer. In the control zone, the region delimited by dotted lines corresponds substantially to that of the grid conducting zone 17.
Alors que la structure représentée en figure 2 était une structure de thyristor à commande par effet de champ, on pourrait élaborer une structure analogue de transistor à commande par transistor à effet de champ. While the structure represented in FIG. 2 was a thyristor structure with field effect control, one could develop an analogous structure of transistor with field effect transistor control.
Alors la couche 12 serait une couche continue sans court-circuit d'émetteur et la partie inférieure du substrat serait revêtue d'une couche uniforme 18 de type
N+. D'autre part, pour des dispositifs de grandes dimensions, on pourra prévoir que le transistor DMOS commande l'étage pilote d'un montage de type Darlington ou thyristor à amplification de gâchette ou équivalent.Then the layer 12 would be a continuous layer without emitter short-circuit and the lower part of the substrate would be coated with a uniform layer 18 of the type
N +. On the other hand, for large devices, provision may be made for the DMOS transistor to control the pilot stage of a Darlington type or thyristor with gate amplification or equivalent.
La présente invention n'est pas limitée aux modes de réalisation qui ont été explicitement décrits. The present invention is not limited to the embodiments which have been explicitly described.
Elle en inclut les diverses variantes et généralisations comprises dans le domaine des revendications ci-après. It includes the various variants and generalizations thereof included in the field of claims below.
Claims (7)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR8016923A FR2488046A1 (en) | 1980-07-31 | 1980-07-31 | DMOS controlled semiconductor power device - uses DMOS FET to drive thyristor with photodiodes deposited on insulating layer with power device using most of substrate area |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR8016923A FR2488046A1 (en) | 1980-07-31 | 1980-07-31 | DMOS controlled semiconductor power device - uses DMOS FET to drive thyristor with photodiodes deposited on insulating layer with power device using most of substrate area |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| FR2488046A1 true FR2488046A1 (en) | 1982-02-05 |
| FR2488046B1 FR2488046B1 (en) | 1984-08-24 |
Family
ID=9244756
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| FR8016923A Granted FR2488046A1 (en) | 1980-07-31 | 1980-07-31 | DMOS controlled semiconductor power device - uses DMOS FET to drive thyristor with photodiodes deposited on insulating layer with power device using most of substrate area |
Country Status (1)
| Country | Link |
|---|---|
| FR (1) | FR2488046A1 (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2524710A1 (en) * | 1982-04-01 | 1983-10-07 | Gen Electric | Control device for bipolar transistor switch - has significantly varying doping concentrations in different semiconductor layers |
| EP0091094A2 (en) * | 1982-04-05 | 1983-10-12 | General Electric Company | Insulated gate rectifier with improved current-carrying capability |
| FR2538170A1 (en) * | 1982-12-21 | 1984-06-22 | Int Rectifier Corp | SEMICONDUCTOR ALTERNATING CURRENT RELAY CIRCUIT AND ASSOCIATED THYRISTOR STRUCTURE |
| EP0118007A2 (en) * | 1983-02-04 | 1984-09-12 | General Electric Company | Electrical circuit comprising a hybrid power switching semiconductor device including an SCR structure |
| EP0118309A2 (en) * | 1983-03-03 | 1984-09-12 | Texas Instruments Incorporated | Semi conductor device and starter circuit for a fluorescent tube lamp, provided with such a semi conductor device |
| EP0190423A2 (en) * | 1984-11-29 | 1986-08-13 | Kabushiki Kaisha Toshiba | Planar semiconductor device having a field plate electrode |
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| US3328604A (en) * | 1964-08-27 | 1967-06-27 | Rca Corp | Integrated semiconductor logic circuits |
| US3433677A (en) * | 1967-04-05 | 1969-03-18 | Cornell Aeronautical Labor Inc | Flexible sheet thin-film photovoltaic generator |
| FR2110299A1 (en) * | 1970-10-08 | 1972-06-02 | Matsushita Electric Ind Co Ltd | |
| FR2181052A1 (en) * | 1972-04-20 | 1973-11-30 | Ncr Co | |
| FR2422258A1 (en) * | 1978-01-19 | 1979-11-02 | Radiotechnique Compelec | Monolithic semiconductor with MOS and bipolar transistors - has FET type input transistor with identical superficial zones as output transistor |
| EP0014435A1 (en) * | 1979-02-06 | 1980-08-20 | Siemens Aktiengesellschaft | Thyristor controlled by field effect transistor |
| EP0017980A1 (en) * | 1979-04-19 | 1980-10-29 | Siemens Aktiengesellschaft | Thyristor controlled by a field-effect transistor |
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- 1980-07-31 FR FR8016923A patent/FR2488046A1/en active Granted
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| US3328604A (en) * | 1964-08-27 | 1967-06-27 | Rca Corp | Integrated semiconductor logic circuits |
| US3433677A (en) * | 1967-04-05 | 1969-03-18 | Cornell Aeronautical Labor Inc | Flexible sheet thin-film photovoltaic generator |
| FR2110299A1 (en) * | 1970-10-08 | 1972-06-02 | Matsushita Electric Ind Co Ltd | |
| FR2181052A1 (en) * | 1972-04-20 | 1973-11-30 | Ncr Co | |
| FR2422258A1 (en) * | 1978-01-19 | 1979-11-02 | Radiotechnique Compelec | Monolithic semiconductor with MOS and bipolar transistors - has FET type input transistor with identical superficial zones as output transistor |
| EP0014435A1 (en) * | 1979-02-06 | 1980-08-20 | Siemens Aktiengesellschaft | Thyristor controlled by field effect transistor |
| EP0017980A1 (en) * | 1979-04-19 | 1980-10-29 | Siemens Aktiengesellschaft | Thyristor controlled by a field-effect transistor |
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Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2524710A1 (en) * | 1982-04-01 | 1983-10-07 | Gen Electric | Control device for bipolar transistor switch - has significantly varying doping concentrations in different semiconductor layers |
| EP0091094A2 (en) * | 1982-04-05 | 1983-10-12 | General Electric Company | Insulated gate rectifier with improved current-carrying capability |
| EP0091094A3 (en) * | 1982-04-05 | 1986-03-26 | General Electric Company | Insulated gate rectifier with improved current-carrying capability |
| FR2538170A1 (en) * | 1982-12-21 | 1984-06-22 | Int Rectifier Corp | SEMICONDUCTOR ALTERNATING CURRENT RELAY CIRCUIT AND ASSOCIATED THYRISTOR STRUCTURE |
| EP0118007A2 (en) * | 1983-02-04 | 1984-09-12 | General Electric Company | Electrical circuit comprising a hybrid power switching semiconductor device including an SCR structure |
| EP0118007A3 (en) * | 1983-02-04 | 1986-06-25 | General Electric Company | Hybrid power switching semiconductor devices including scr structures |
| EP0118309A2 (en) * | 1983-03-03 | 1984-09-12 | Texas Instruments Incorporated | Semi conductor device and starter circuit for a fluorescent tube lamp, provided with such a semi conductor device |
| EP0118309A3 (en) * | 1983-03-03 | 1984-11-14 | Texas Instruments Incorporated | Starter circuit for a fluorescent tube lamp |
| EP0190423A2 (en) * | 1984-11-29 | 1986-08-13 | Kabushiki Kaisha Toshiba | Planar semiconductor device having a field plate electrode |
| EP0190423A3 (en) * | 1984-11-29 | 1988-01-27 | Kabushiki Kaisha Toshiba | Planar semiconductor device having a field plate electrode |
Also Published As
| Publication number | Publication date |
|---|---|
| FR2488046B1 (en) | 1984-08-24 |
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