JPH09260715A - Photodiode built-in semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To lessen a parasitic capacity due to a depletion layer and thereby increase a response speed by forming a p-type well region between an epitaxial layer and an isolation region, which constitute a photodiode. SOLUTION: A p-type well region 24 which has a lower impurity concentration than an isolation region 13 is formed over the p+ isolation region 13 which partitions a photodiode section. It is preferred that the well region 24 passes through an epitaxial layer 12. Then, by applying a reverse bias voltage between an anode electrode 23 and a cathode electrode 16, a depletion layer 25 is formed in a PN junction which constitutes a photodiode. By this method, the depletion layer 25 can be expanded to the epitaxial layer 12 side which has a low impurity concentration and even into the p-type well region 25, formed adjacently to the isolation region 13. Therefore, a parasitic capacity which depends on the width of the depletion layer 25 can be remarkably lessened.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to improving the response speed of a photodiode in a semiconductor integrated circuit incorporating the photodiode.

[0002]

2. Description of the Related Art A monolithic optical semiconductor integrated circuit device in which a photodiode, which is a light receiving element, and its peripheral circuit are integrated is manufactured separately, and a significant cost reduction can be realized as compared with a hybridized integrated circuit device. It also has a strong advantage against external noise caused by electromagnetic fields.

As a conventional optical semiconductor integrated circuit device, for example, one described in Japanese Patent Application Laid-Open No. 1-205564 is known. A conventional optical semiconductor integrated circuit device will be described with reference to FIG. In FIG. 2, 1 is a P-type semiconductor substrate, 2
Is an N-type epitaxial layer, 3 is a P + type isolation region,
4 is an N + type cathode extraction diffusion region, 5 is a cathode electrode, 6 is a silicon oxide film, and 7 is P of an NPN transistor.
A type base region, 8 is an N + type emitter region of an NPN transistor, and 9 is an N + type buried layer.

In such a structure, the P formed between the semiconductor substrate 1 and the epitaxial layer 2 surrounded by the isolation region 3 is formed.
The N junction is used as a photodiode. In this photodiode, carriers generated by light incident on the epitaxial layer 2 are detected as a current from the cathode electrode 6 in ohmic contact with the cathode extraction diffusion region 5 and used.

[0005]

However, in the optical semiconductor integrated circuit device having such a structure, the parasitic capacitance is inevitably formed by the depletion layer 10. Therefore, the larger the parasitic capacitance is, the worse the frequency characteristic of the photodiode PD becomes. There is a problem that impedes high-speed operation. Especially P + isolation region 3
In this case, the depletion layer 10 does not spread because it is formed with a relatively high impurity concentration for the purpose of separating elements.
This is a cause of increasing the parasitic capacitance.

[0006]

SUMMARY OF THE INVENTION The present invention has been made in view of the above conventional problems, and a parasitic region is formed by forming a P-type well region between an epitaxial layer forming a photodiode and an isolation region. Provided is a semiconductor integrated circuit with a built-in photodiode, which has a reduced capacity and an improved response speed.

According to the present invention, since the epitaxial layer originally has a low impurity concentration and the P− type well region is formed between the P + isolation region and the N type epitaxial layer, the PN forming the photodiode is formed. The junction becomes a P- / N type junction, the parasitic capacitance due to the depletion layer is reduced, deterioration of the frequency characteristics of the photodiode can be eliminated, and high-speed operation can be realized.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings. FIG. 1 is a sectional view showing a semiconductor integrated circuit incorporating a photodiode according to the present invention. In FIG. 1, 11 is a P-type semiconductor substrate, 12 is an N-type epitaxial layer, 13 is a P + type isolation region, 14 is an island region composed of the epitaxial layer 12 separated by the P + isolation region 13, and 15 is an island region. N + type cathode extraction diffusion region formed on the surface of 14; 16 a cathode electrode which makes ohmic contact with the surface of the cathode extraction diffusion region;
7 is a silicon oxide film.

A signal processing section represented by an NPN transistor is formed on the same substrate as the photodiode. 18
Is a P-type base region formed on the surface of the island region 12 serving as a collector, and 19 is N + formed on the surface of the base region 18.
A type emitter region, 20 is a base electrode, 21 is an emitter electrode, and 22 is an N + type buried layer. The P-type semiconductor substrate 11 is a silicon single crystal substrate, has a specific resistance of several Ω · cm when the semiconductor integrated circuit device is completed, and mechanically supports the semiconductor integrated circuit device. Thirty
It is formed as thick as 0 micron or more.

The N 1 -type epitaxial layer 12 is grown on the semiconductor substrate 11 by phosphorus (P) doping by vapor phase epitaxy, and is laminated to have a specific resistance of several Ω · cm or more and a thickness of several μ.
This thickness is selected to be optimum depending on the incident light. Further, the impurity concentration of the epitaxial layer 12 may be set to the optimum value for the photodiode, and the NPN transistor may be diffused with N-type impurities in a portion serving as a collector to compensate for the insufficient impurity concentration.

The N + type cathode extraction diffusion region 15 is formed on the upper surface of the epitaxial layer 12 at the same time as the diffusion of the emitter region 19 of the NPN transistor by the selective diffusion method. An aluminum cathode electrode 16 in ohmic contact is provided in the cathode extraction diffusion region 15. The anode electrode 23 contacts the surface of the P + type isolation region 13 around the cathode extraction diffusion region 15.

The P + isolation region 13 for partitioning the photodiode portion is overlapped, and P having a lower impurity concentration than the isolation region 13 is formed.
A negative well region 24 is formed. This well area 24
Preferably penetrates the epitaxial layer 12,
To the middle of the process, for example, as a separation region 13, a vertical separation method is used to connect a diffusion layer upward from the surface of the substrate 11 and a diffusion region downward from the surface of the epitaxial layer 12 to the same extent as the downward diffusion region. You may end at the depth of. Further, the P− type well region 24 may be present only inside the separation region 13 so as to surround the cathode extraction diffusion region 15.

Then, by applying a reverse bias such as +5 V to the anode electrode 23 and the cathode electrode 16, the depletion layer 25 is formed in the PN junction forming the photodiode. When light is incident on the depletion layer 25 from the outside, photocurrent is generated, and the anode / cathode electrodes 16 and 23 are generated.
According to the present invention in which a signal current flows between them, the depletion layer 25 can be expanded to the side of the epitaxial layer 12 originally having a low impurity concentration, and the P− formed adjacent to the isolation region 13 is formed. The well region 25 can be expanded inside. Therefore, even when the same reverse bias as in the conventional case is applied, the parasitic capacitance of the photodiode, which can be formed in the width of the depletion layer 25, can be significantly reduced.

[0014]

As described above, according to the present invention, the P-type well region 24 formed adjacent to the isolation region 13 is formed.
Since the depletion layer 25 can be expanded to the inside of the, the width of the depletion layer 25 that expands toward the isolation region 13 side can be increased compared to the conventional case. Therefore, the parasitic capacitance of the photodiode can be reduced, and the high speed response of the photodiode can be improved.

[Brief description of drawings]

FIG. 1 is a cross-sectional view for explaining a photodiode integrated semiconductor integrated circuit of the present invention.

FIG. 2 is a cross-sectional view for explaining a conventional semiconductor integrated circuit with a built-in photodiode.

Claims (2)

[Claims] 1. A semiconductor substrate of one conductivity type, an epitaxial layer of an opposite conductivity type formed on the semiconductor substrate, and one conductivity which penetrates the epitaxial layer and separates the epitaxial layer into a plurality of island regions. Type isolation region, the island region and the isolation region, and the PN junction between the isolation region and the substrate as a photodiode, the potential is applied to the island region and the isolation region to reverse bias the photodiode, respectively. In a semiconductor integrated circuit with a built-in photodiode including an electrode to be applied, a well region of one conductivity type having an impurity concentration lower than that of the isolation region is formed between the isolation region and the island region. Semiconductor integrated circuit. 2. The semiconductor integrated circuit with a built-in photodiode according to claim 1, wherein the well region of one conductivity type extends from the surface of the epitaxial layer to the surface of the substrate.