JP2521745Y2 - Photo thyristor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial application field) The present invention relates to a structure for obtaining high reliability of a vertical photothyristor used for ignition.

(Prior Art) FIG. 3 is a schematic sectional view of a conventional vertical photothyristor based on the planar technique. A P gate diffusion layer 3 is formed on the surface of the N-type semiconductor substrate 1, and a cathode diffusion layer 4 is formed on a part of the P gate diffusion layer. An anode diffusion layer 2 is formed on a side portion and a back surface of the N-type semiconductor substrate 1.
An N ⁺ type diffusion layer 5 is formed on the surface of the type semiconductor substrate 1 between the P gate diffusion layer 3 and the anode diffusion layer 2 and functions as a guard ring or a channel stopper. Furthermore, N
The surface of the type semiconductor substrate 1 is covered with an oxide film 6 except for the surface of the cathode diffusion layer 4, and the surface of each PN junction is covered with an Al electrode 7. In such a vertical photothyristor, a P gate diffusion layer 3, an N type semiconductor substrate 1,
The h _FE of the PNP transistor composed of the anode diffusion layer 2 is N
_HFE (PNP) in the vertical direction perpendicular to the semiconductor substrate 1
And _hFE (PNP) in the horizontal direction.

(Problem to be Solved by the Invention) In the conventional structure as described above, in the vertical _hFE (PN
P) is determined by the distance between the P gate diffusion layer 3 on the front surface and the anode diffusion layer 2 on the rear surface, and is hardly affected by external influences and has little fluctuation. However, the lateral _hFE (PNP) is
The fluctuation is relatively large under the influence of the interface state between the N-type semiconductor substrate 1 and the insulating film covering the same, for example, the oxide film 6. In the manufacturing process, h _FE (P
NP) is affected, and the lateral _hFE (PNP) fluctuates further. This variation in the lateral direction of the h _FE (PNP), also vary h _FE of the PNP transistor, the minimum input current required I _FT (SSR are electrical characteristics of the thyristor is shifted from the OFF state to the ON state ) Fluctuates.

(Means for Solving the Problems) The N-type semiconductor substrate 1 is provided at the interface between the P-gate diffusion layer 3 and the anode diffusion layer 2 on the surface of the N-type semiconductor substrate 1 and the insulating film on the surface of the N-type region. An N-type diffusion layer having an impurity concentration higher than the impurity concentration is formed.

(Operation) The N-type diffusion layer of the above, it is possible to suppress variation in the interface state between the oxide film of the N-type semiconductor substrate surface between the surface and the surface of the anode diffusion layer of the P-gate diffusion layer, I _FT Is also suppressed.

(Embodiment) FIG. 1 is a schematic sectional view of an embodiment of the present invention. As the N-type semiconductor substrate 1, for example, a substrate having an impurity concentration of 1 × 10 ¹⁴ cm ⁻³ is used. A P gate diffusion layer 3 is formed substantially at the center of this surface, and a cathode diffusion layer 4 is formed on a part of the surface.
An anode diffusion layer 2 is formed on a side portion and a back surface of the N-type semiconductor substrate 1. An N ⁺ type diffusion layer 5 acting as a guard ring is formed between the P gate diffusion layer 3 and the anode diffusion layer 2 on the surface of the N type semiconductor substrate 1. The N ⁺ type diffusion layer 5 is formed simultaneously with the cathode diffusion layer 4. Well-known photoetching and impurity diffusion techniques are used to form these diffusion layers. The impurity concentration of the anode diffusion layer 2 and the P gate diffusion layer 3 is, for example, 1 × 10 ¹⁸ cm ⁻³ ,
The impurity concentration of the cathode diffusion layer 4 is, for example, 1 × 10 ²⁰ cm ⁻³ . The structure so far is the same as the structure of the conventional example shown in FIG. 3, but in the present invention, the surface of the N-type semiconductor substrate 1 between the P gate diffusion layer 3 and the anode diffusion layer 2 is provided with an N-type semiconductor substrate. An N-type diffusion layer 8 is formed which is slightly higher than the impurity concentration of No. 1 and which can maintain the withstand voltage, for example, about 2-3 × 10 ¹⁴ cm ^-3 . At this time, it is convenient to use an ion implantation method to control the concentration. Thereafter, the surface of the substrate is covered with the oxide film 6 and the surface of the PN junction is covered with the Al electrode 7 as in the conventional example.

FIG. 2 is a schematic cross-sectional view of another embodiment. In this case, the N-type diffusion layer 8 also covers the surfaces of the end portions of the P gate diffusion layer 3 and the anode diffusion layer 2. However, in this structure, the depletion layer may be bent, but the effect of preventing the influence of the interface state is great.

As is clear from FIGS. 1 and 2, the depth of the N-type diffusion layer 8 is smaller than the depth of the N ⁺ -type diffusion layer 5.

As above (Effect of invention), according to the merits, since it is possible to reduce fluctuations in the lateral direction h _FE (PNP), good photothyristor stability of I _FT is obtained. Further, since the impurity concentration on the surface of the N-type semiconductor substrate 1 between the P gate diffusion layer 3 and the anode diffusion layer 2 can be controlled in the process, the selection range of the wafer is expanded.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view of one embodiment of the present invention, FIG. 2 is a schematic sectional view of another embodiment, and FIG. 3 is a schematic sectional view of a conventional example. 1 ... N-type semiconductor substrate, 2 ... Anode diffusion layer, 3 ...
P gate diffusion layer, 4 ... Cathode diffusion layer, 8 ... N-type diffusion layer

Claims (1)

(57) [Scope of request for utility model registration] 1. An impurity concentration higher than the impurity concentration of an N-type semiconductor substrate over an entire interface between an N-type region between a P-gate diffusion layer and an anode diffusion layer on the surface of the N-type semiconductor substrate and an insulating film on the surface. , Lower than the impurity concentration of the cathode diffusion layer and shallower than the depth of the N-type diffusion layer acting as a guard ring.
A photothyristor with a mold diffusion layer.