JP2604793B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to an improvement of a so-called I ² L semiconductor device in which a horizontal transistor and a vertical transistor are combined.

[Conventional technology]

The factor that greatly affects the gate delay per stage in I ² L is the accumulated charge of minority carriers in the unnecessary epi region. Therefore, in order to increase the speed of I ² L, a method of forming a base exclusively for I ² L separately from a base of a transistor used in a linear circuit formed on the same substrate has been conventionally performed. (Hereinafter, this is referred to as an I ² L base.) In order to minimize the unnecessary area in the vertical direction, the I ² L base is desirably as deep as possible. Further, it is desirable to increase the current gain by lowering the concentration of the I ² L base region in order to avoid the influence of the decrease in the current gain due to the temperature.

FIG. 2 shows such a conventional I ² L structure. In the structure of FIG. 2, the unnecessary epi regions in the lateral direction are minimized by forming an oxide film.

[Problems to be solved by the invention]

FIG. 3 shows the profile of the inverter section in the above-described conventional structure. Generally, when the epi thickness is 4 μm, the appropriate depth of the I ² L base is 1.5 to ² μm. In this case, the peak concentration of the I ² L base is 5 × 10 ¹⁶ to 1 × 1.
0 ¹⁷ cm ^-3 . However, in such a profile, I
^{Since the 2} L base is formed by using the ion implantation technique, the surface concentration of the base is reduced (5 × 10 ¹⁵ to 1 × 10 ¹⁶ cm ⁻³ ). Therefore, when the inverter is configured as shown in FIG.
As shown in FIG. 2B, there is a disadvantage that a parasitic MOS is generated between the collector and the emitter due to the Al wiring extending from the collector, and the withstand voltage between CEs is reduced.

[Means for solving the problem]

In a semiconductor device of the present invention, in an I ² L structure including a lateral PNP transistor and a vertical NPN transistor, a junction having a higher concentration and a shallower junction around the P-type base region of the vertical NPN transistor than the base region. It has some P-type regions.

〔Example〕

FIG. 1 is a plan view and a longitudinal sectional view of one embodiment of the present invention.

FIG. 1 shows only the inverter section constituting I ² L. An N-type buried layer 102 is formed on a P-type semiconductor substrate 101, and an N-type epitaxial layer 103 is formed. I ² L base 104
After forming an oxide film 107 for insulation isolation, I ² L
A P-type region 105 is provided around the base 104 so that the junction becomes higher in concentration and shallower than the I ² L base. FIG. 5 shows the profiles of the I ² L base 104 and the high-concentration P-type diffusion layer 105. I ² L
The peak concentration of the base is 5 × 10 ¹⁶ to 1 × 10 ¹⁷ cm ⁻³ , whereas the peak concentration of the P-type diffusion layer 105 is preferably 10 ¹⁸ to 10 ¹⁹ cm ⁻³ . It is appropriate that the depth is about 1/2 of the I ² L base. The P-type region 105 also serves as a lead-out region for the base electrode 109. Also, linear parts mixed on the same chip
It may be formed simultaneously with the base region of the NPN transistor. Thereafter, the N-type high concentration region 106 serving as a collector region is formed.
Are formed and the respective electrodes are provided to form an I ² L inverter.

〔The invention's effect〕

As described above, according to the present invention, low concentration and deep I ² L
In a high-speed I ² L structure having a base, a threshold voltage of a parasitic MOS can be increased by providing a P-type region having a higher concentration than the I ² L base 104 around the periphery, thereby improving the breakdown voltage of the I ² L. Can be. In addition, by making this high-concentration P-type region shallower than the I ² L base, an increase in capacitance is not likely.

[Brief description of the drawings]

1 (a), 1 (b) and 1 (c) are a plan view and a longitudinal sectional view of a semiconductor device of the present invention, FIGS. 2 and 4 (a) and (b) are longitudinal sectional views of a conventional structure, FIG. 3 shows an impurity profile of a conventional structure, and FIG. 5 shows an impurity profile according to the present invention. 101,201 ... P-type silicon substrate, 102,203 ... High-concentration N-type buried layer, 103,205 ... N-type epitaxial layer, 104,208 ...
... P-type I ² L base region, 105 ... high-concentration P-type region, 106 ...
... High-concentration N-type region, 107,206 ... Oxide film, 108 ... Collector electrode, 109 ... Base electrode, 202 ... P-type diffusion region
204: N-type diffusion region, 207: P-type base region, 209:
... N-type emitter region, 210 ... Al electrode wiring.

Claims (1)

(57) [Claims] 1. An I ² L structure comprising a horizontal PNP transistor and a vertical NPN transistor, wherein the vertical N
A semiconductor device provided in a P-type base region of a PN transistor, surrounding a collector region, having a P-type region having a higher concentration than the base region and shallower than the base region.