JPH10270458A - Lateral bipolar transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a lateral bipolar transistor having a high hfe . SOLUTION: In a lateral bipolar transistor provided with a P-type emitter area and a collector area 8 on the surface of an N-type semiconductor area constituting a base area 3, an emitter electrode 10 and another electrode having the same potential as an electrode 10 has are provided on the surface of the base area 3 with an insulating film 6 in between. In addition, a P- or N-type injected area 13 is provided by implanting the ion of a P- or N-type impurity into the area corresponding to the maximum depletion layer width on the surface of the base area 3. In the lateral bipolar transistor having the above- mentioned structure, carriers run through the P- or N-type injected area 13.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a lateral bipolar transistor, and more particularly to a lateral bipolar transistor having a high hfe.

[0002]

2. Description of the Related Art The structure of a conventional lateral PNP bipolar transistor is shown in FIG. In the figure, 1 is a P-type silicon substrate, 2 is an N-type buried layer, 3 is a base region made of an N-type epitaxial layer, 4 is a LOCOS oxide film, 5 is a channel stopper made of a P-type diffusion region, 6 is an insulating film, Reference numeral 7 denotes an emitter region formed of a P-type diffusion region, 8 denotes a collector region formed of a P-type diffusion region, 9 denotes a base contact region formed of an N-type diffusion region, 10 denotes an emitter electrode, 11 denotes a collector electrode, and 12 denotes a base electrode. .

In the lateral PNP bipolar transistor having such a structure, a current component flowing in a lateral direction parallel to the surface of the base region 3 among minority carriers injected from the emitter region 7 contributes to the transistor operation. However, the surface of the base region 3 serving as the current path has many crystal defects and the like, and recombination of carriers is likely to occur. Therefore, the ground emitter current amplification factor hfe of the lateral bipolar transistor is generally smaller than the hfe of the vertical bipolar transistor.

Conventionally, as a method for increasing the hfe of a lateral bipolar transistor, the distance between the emitter region 7 and the collector region 8 is reduced, the base width is reduced, and the diffusion region forming the emitter region 7 and the collector region 8 is deepened. A structure to be formed has been proposed.

[0005]

However, if the base width is reduced to increase hfe, there is a problem that the withstand voltage is degraded, the manufacturing process becomes complicated, and the manufacturing cannot be performed with good reproducibility. . Also, the method of forming the emitter and collector regions deeply has a problem that it is difficult to control the manufacturing process. An object of the present invention is to solve the above problems and to provide a lateral bipolar transistor having a high hfe.

[0006]

According to the present invention, in order to achieve the above object, a semiconductor region of one conductivity type is provided with an emitter region and a collector region of opposite conductivity type, and the one region between the emitter region and the collector region is provided. In a lateral bipolar transistor having a semiconductor region of a conductivity type as a base region, an electrode having the same potential as an emitter electrode connected to the emitter region via an insulating film on the surface of the base region, and a maximum determined by an impurity concentration of the base region. A region corresponding to the width of the depletion layer is provided with a reverse conductivity type or one conductivity type injection region having the maximum impurity concentration, and the carrier mainly travels in the injection region.

[0007] By forming the position where the impurity concentration of the reverse conductivity type or the one conductivity type injection region is maximized at a deep position, recombination of carriers and the like can be suppressed.
A configuration that does not cause a decrease in fe can be achieved.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The embodiments of the present invention will be described below using a lateral PNP transistor as an example. FIG. 1 shows the structure. In the figure, 1 is a P-type silicon substrate, 2 is an N-type buried layer, 3 is a base region made of an N-type epitaxial layer, 4 is a LOCOS oxide film, 5 is a channel stopper made of a P-type diffusion region, 6 is an insulating film, 7 is an emitter region formed of a P-type diffusion region, 8 is a collector region formed of a P-type diffusion region, 9 is a base contact region formed of an N-type diffusion region, 10 is an emitter electrode, 12 is a base electrode, and 13 is a P-type impurity. Is an impurity-implanted region formed by injecting impurities.

As shown in the figure, in a lateral PNP transistor of the present invention, an impurity implanted region 13 is formed on the surface of a base region 3 between an emitter region 7 and a collector region 8. The impurity-implanted region 13 is configured to exhibit a P-type conductivity at a low concentration or an N-type conductivity having a sufficiently lower impurity concentration than the N-type epitaxial layer forming the base region 3 depending on implantation conditions. It can be configured as follows.

Here, the position where the impurity concentration of the impurity-implanted region 13 is maximum is determined at a predetermined position by the concentration of the N-type epitaxial layer constituting the base region. That is, assuming that a MOS transistor is formed in a semiconductor region having the same impurity concentration as the N-type epitaxial layer,
The position where the impurity concentration becomes maximum is arranged near the depletion layer width immediately before the accumulation of carriers calculated when a voltage is applied to the gate electrode, that is, near the depth corresponding to the maximum depletion layer width. Assuming that the emitter electrode 10 of FIG. 1 constitutes a gate electrode, the insulating film 6 constitutes a gate oxide film, and the N-type epitaxial layer of the base region 3 constitutes a channel region,
The maximum depletion layer width of the OS transistor is calculated.

Further, the emitter electrode 10 is connected to the base region 3.
It is arranged on the surface via an insulating film 6. This base area 3
The electrode disposed on the surface is not necessarily required to be integral with the emitter electrode 10, but is configured so that the same potential as the emitter electrode 10 is applied.

In the lateral PNP transistor having such a structure, when a potential difference is generated between the emitter and the base in accordance with the operating conditions, the surface of the base region 3 is depleted. Since impurity implantation region 13 is located in the region where the depletion layer is formed, when the conductivity type of impurity implantation region 13 is P-type, holes mainly travel in the implantation region. Become. When the impurity-implanted region 13 is N-type, the carrier travels in the impurity-implanted region since the impurity concentration is lower than that of the N-type epitaxial layer forming the base region 3.

[0013] Since the carrier travels not at the surface where the carrier recombination occurs but at a deep position, recombination of the carrier does not occur and the high current amplification factor h is obtained.
You can get fe.

A lateral PNP transistor having such a structure can be formed as follows. First, P
In order to form the N-type buried layer 2 on the surface of the silicon substrate 1,
Impurity ions are implanted to grow an N-type epitaxial layer. Thereafter, a P-type diffusion layer serving as a channel stopper 5 is formed, a nitride film is formed on the surface of the N-type epitaxial layer, thermal oxidation is performed, and LOCO is formed on the surface excluding the element formation region.
An S oxide film 4 is formed. Thereafter, a base contact region 9 composed of an N-type diffusion region reaching the previously formed N-type buried layer 2 is formed, and forms a part of the base region together with the N-type buried layer 2.

After the oxide film on the surface where the emitter and collector are to be formed is once removed to expose the surface of the N-type epitaxial layer, an insulating film 6 of about 400 to 750 Å is formed by thermal oxidation. Boron ions having a conductivity type opposite to that of the N-type epitaxial layer forming the base region are implanted through the insulating film 6 to form the impurity implanted region 13 (FIG. 2).

Here, in the impurity implanted region 13 formed by implanting boron ions, the position where the impurity concentration becomes maximum is determined at a predetermined position by the concentration of the N-type epitaxial layer constituting the base region. That is, assuming that a MOS transistor is formed in a semiconductor region having the same impurity concentration as the N-type epitaxial layer, the depletion layer width immediately before the accumulation of carriers calculated when a voltage is applied to the gate electrode, that is, the maximum depletion layer width is set. Near the depth of the corresponding dimension,
The position where the impurity concentration becomes maximum is arranged.

As an example, the impurity concentration is 2.5 × 10 15
FIG. 3 shows a case where boron ions are implanted into an N-type epitaxial layer of atom / cm 3 through an insulating film made of 400 Å of silicon dioxide under the conditions of an acceleration energy of 30 KeV and a dose of 2.5 × 10 11 atoms / cm 2. Thus, an impurity-implanted region having a maximum impurity concentration at a position of 600 Å from the surface is formed. The maximum depletion layer width calculated from the impurity concentration of the N-type epitaxial layer is 1000 Å.

Thereafter, in the same manner as in the conventional manufacturing method, boron ions are implanted at an energy of 70 KeV and a dose of 3.6.times.10 to form the emitter region 7 and the collector region 8.
It is selectively implanted under the condition of 14 / cm 2, and thermal diffusion is performed at 1000 ° C. for 2 hours. Emitter electrode 1 made of aluminum or the like connected to the emitter, collector and base regions
0, a collector electrode (not shown) and a base electrode 12 are formed (FIG. 1). Here, the emitter electrode 10 is formed on the base region 3 between the emitter region 7 and the collector region 8 so as to extend through the insulating film 6. Note that the electrode extending over the base region does not necessarily need to be formed integrally with the emitter electrode, but at least has the same potential as the emitter electrode.

As described above, the carrier travels not at the surface where the carrier recombination occurs but at a deep position, so that a high current amplification factor hfe can be obtained. Specifically, the impurity concentration of the N-type epitaxial layer is 2.5 × 10
In the 15 atom / cm 3 transistor, when no boron ions were implanted, the hfe was 100, but the acceleration voltage was 30 KeV, the implantation amount was 1.8 × 10 11,
When boron ions are implanted under the conditions of 2.4 × 10 11 and 3.0 × 10 11 / cm 2, hfe is 230, 55 respectively.
It was confirmed to be 0, 2500. Further, the withstand voltage between the collector and the emitter was 20 V or more, and it was confirmed that the withstand voltage did not decrease by boron ion implantation.

Since the depth at which the impurity concentration of boron ions becomes maximum is only required to be shallower than the depth corresponding to the above-described maximum depletion layer width, implantation conditions may be appropriately set. However, since recombination of carriers occurs near the surface, it is preferable to form the layer near the depth corresponding to the maximum depletion layer width. On the other hand, if it is deeper than the depth corresponding to the maximum depletion layer width, the leakage current between the emitter and the collector increases, which is not preferable. Furthermore, the result that the withstand voltage between the emitter and the collector is lowered is not preferable.

Although the PNP transistor has been described above, it goes without saying that the same effect can be obtained with the NPN transistor.

[0022]

As described above, according to the present invention, hfe can be obtained without lowering the breakdown voltage of the lateral transistor.
Could be greatly improved. Since the manufacturing method is based on a normal semiconductor device manufacturing process, it is advantageous in that it can be manufactured with good reproducibility.

[Brief description of the drawings]

FIG. 1 is a sectional view of a lateral PNP transistor according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating a method for manufacturing a lateral PNP transistor according to an embodiment of the present invention.

FIG. 3 is a graph illustrating an embodiment of the present invention.

FIG. 4 is a sectional view of a conventional lateral PNP transistor.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 P-type silicon substrate 2 N-type buried layer 3 base region 4 LOCOS oxide film 5 channel stopper 6 insulating film 7 emitter region 8 collector region 9 base contact region 10 emitter electrode 11 collector electrode 12 base electrode 13 impurity implantation region

Claims (1)

[Claims] 1. A lateral bipolar transistor having an emitter region and a collector region of opposite conductivity type in a semiconductor region of one conductivity type, and using the semiconductor region of one conductivity type between the emitter region and the collector region as a base region. An electrode having the same potential as an emitter electrode connected to the emitter region via an insulating film on the surface of the base region, and a maximum impurity concentration in a region corresponding to a maximum depletion layer width determined by the impurity concentration of the base region. A lateral bipolar transistor comprising: a reverse conductivity type or one conductivity type injection region having: and a carrier mainly traveling in the injection region.