JP2650405B2 - Bipolar transistor - Google Patents

Description

Description: BACKGROUND OF THE INVENTION The present invention relates to a bipolar transistor suitable for a high breakdown voltage transistor for an integrated circuit device or the like, in which a collector region of one conductivity type and another conductive region in a collector region are provided. A base region formed in a shape and an emitter region formed in the base region in one conductivity type.

[Conventional technology]

As is well known, a bipolar transistor is a basic circuit element widely used for a bipolar type or BiMOS type integrated circuit device, etc.In recent years, in many cases, a load is driven by incorporating a bipolar transistor on its output side. It has become. Accordingly, bipolar transistors often require high withstand voltage and high current performance, and various contrivances have conventionally been made. 4 and 5 show a typical conventional structure.

Fig. 4 shows a graph and base suitable for high withstand voltage
The figure shows a state in which an n transistor is incorporated in an integrated circuit device. After a buried layer 2 is diffused in a strong n-type in advance in a predetermined area on the surface of a p-type substrate 1 for an integrated circuit device, an epitaxial layer 3 is grown in an n-type and surrounds a predetermined area from the surface. The epitaxial layer 3 is junction-separated from the substrate 1 into an island-shaped region by deeply diffusing the isolation layer 4 so as to reach the substrate 1 with a strong p-type, and this region is used as a collector region to form a bipolar transistor.

Since the transistor in the figure is a vertical transistor, a strong n-type low-resistance layer 5 is deeply diffused and connected to the buried layer 2 in order to lead the collector terminal C from the buried layer 2. Next, the p-type graft base region 6 is deeply diffused with a low impurity concentration in an annular pattern surrounding a range where the base region 8 is to be formed, and the p-type base region 8 is overlapped with its inner peripheral edge. It diffuses shallower than that, and further forms an emitter region 9 with a strong n-type inside. The terminals for the collector C, the base B, and the emitter E are formed by making the metal electrode film, which is omitted from the drawing for simplicity, into conductive contact with the surface of the corresponding region in the window opened in the insulating film 10 such as an oxide film. Derived.

When a high voltage is applied between the collector terminal C and the base terminal B, as is well known, an electric field concentrates on the bottom peripheral corner of the base region 8 and the breakdown voltage tends to decrease. Since the low impurity concentration graph and the region 6 are deeply diffused so as to surround the portion and the radius of curvature is large, the electric field concentration is reduced and the withstand voltage value is improved.

In FIG. 4, the flow of electrons e is indicated by thin arrows,
The current caused by this flows considerably concentrated not only on the bottom surface of the emitter region 9 but also on the periphery of the bottom as shown in the figure. In the structure of the bipolar transistor shown in FIG. 5, a plurality of emitter regions 9 are formed in the base region 8 in order to increase the current contribution at the bottom peripheral portion of the emitter region 8. A transistor having a current capacity can be formed in a small chip area. Of course, by providing the graph of FIG. 4 and the region 6 on the periphery of the base region 8 of the transistor of FIG. 5, the withstand voltage value can be improved.

[Problems to be solved by the invention]

As described above, the graph of FIG. 4 and the base structure are very effective means for increasing the withstand voltage. However, in order to increase the withstand voltage by this means, the chip area must be increased accordingly. There is a problem, and the chip area becomes considerably large especially when it is desired to increase the withstand voltage to 100 V or more, or to achieve both high withstand voltage and large current capacity.

That is, the graph of FIG. 4 and the region 6 have no effect unless they are formed with a radius of curvature large enough to alleviate the electric field concentration. To this end, the diffusion depth in the vertical direction is made sufficiently large according to the required breakdown voltage. This is because the diffusion also spreads in the horizontal direction. As can be seen from FIG. 4, the graph and the region 6 protrude downward from the bottom of the base region 8 and the flow of electrons e from the bottom corner of the emitter region 9 is hindered by this. Therefore, it is necessary to laterally separate and separate the graft region 6 from the emitter region 9, which further increases the chip area.

Needless to say, there is a similar problem when increasing the breakdown voltage of the bipolar transistor having the large current capacity structure shown in FIG.

The present invention solves such a problem and increases the withstand voltage, particularly 100 V
It is an object of the present invention to obtain a bipolar transistor having a structure suitable for increasing the withstand voltage, reducing the chip area as compared with the conventional one, and at the same time, increasing the current capacity as much as possible.

[Means for solving the problem]

According to the present invention, according to the present invention, a collector region of one conductivity type, an electrode formed in the collector region via an insulating film on the surface thereof, and self-alignment in the collector region from the surface using the electrode as a mask A base region of the other conductivity type and an emitter region of one conductivity type, which are formed so that a peripheral portion of the base region is sunk under the electrode sequentially, and the electrode is continuous with the collector region, the base region, and the base region. This is achieved by applying an electric potential substantially equal to that of the base region to the electrode by opposing the surface of the emitter region including at least a peripheral portion of the emitter region via an insulating film.

It is most preferable that the electrodes in the above structure be made of polycrystalline silicon, like the gate of the field effect transistor. Although this electrode is in principle connected to the base region at an equipotential, it may be desirable to connect the electrode to the emitter region at an equipotential depending on the application circuit. An oxide film is suitable for the insulating film below this electrode, and its thickness may be uniform, but it is more depleted in the collector region if a part of the collector region is formed thicker than the periphery of the base region. It may be desirable to moderate the spreading of the layers.

The present invention is most easily applied to a bipolar transistor having a structure in which a single base region or a plurality of emitter regions are formed in a single base region, and furthermore, a single emitter region is formed in a plurality of base regions. In this case, a stripe-shaped electrode can be commonly provided in adjacent base regions. In the latter case, an annular electrode can be provided so as to surround the base region group from the outside. In some cases, it is advantageous to provide a graft region instead of the annular electrode.

In the present invention, the base region and the emitter region are formed by so-called self-aligned diffusion by an ion implantation method using an electrode corresponding to the gate as a mask as in a field effect transistor. Is provided so as to face the surface of a part of the range including the peripheral edge thereof via an insulating film.

[Action]

As is well known, the withstand voltage of a bipolar transistor is usually the maximum voltage that can be applied between the collector region and the base region when the bipolar transistor is off, and when this voltage is applied, a depletion layer mainly forms from the pn junction surface of both regions. If the depletion layer is not sufficiently expanded, the electric field is concentrated on the bottom corner of the base region, and the breakdown voltage decreases. The present invention promotes the expansion of the depletion layer by the electrodes described above to improve the breakdown voltage, and its operation will be described with reference to FIG.

In FIG. 1 (a), a p-type base region 8 is formed in an n-type collector region 3 as in FIG.
A respective emitter region 9 is formed. The surfaces of these regions are usually covered with a thin insulating film 10, which is an oxide film, and over a range including the periphery of the base region 8, which is a pn junction between the collector region 3 and the surface of the base region 8. An electrode 7 of the present invention made of polycrystalline silicon or the like is provided with the insulating film 10 interposed therebetween.

Further, in the present invention, a potential substantially equal to that of the base region is applied to the electrode 7. Insulating film by the potential of this electrode 7
The spread of the depletion layer DL on the surfaces of the collector region 3 and the base region 8 is affected by the electrostatic induction via 10, but the spread is slightly suppressed on the side of the base region 8 having the same potential as the electrode 7. Is the collector region 3 of the reverse conductivity type
On the side, the opposite is encouraged. On the other hand, the extension of the depletion layer DL into the collector region 3 below the bottom of the base region 8 is, of course, irrelevant to the presence of the electrode 7.

As described above, the spreading of the depletion layer DL in the collector region 3 is not promoted in the vertical direction, but is promoted in the horizontal direction on the surface thereof. As a result, the shape of the depletion layer DL is shown by hatching in the figure. As a result, the radius of curvature R of the bottom corner of the base region 8 becomes much larger than the radius of curvature r of the bottom corner of the base region 8 as shown in the figure, thereby remarkably reducing the electric field concentration. The extent of the depletion layer DL on the surface of the collector region 3 slightly varies depending on the thickness of the insulating film 10, but can be controlled quite accurately by the width of the electrode 7.

As can be seen, the electrode 7 according to the present invention has a function equivalent to that of the conventional graft base region in relaxing the electric field concentration at the bottom corner of the base region and improving the breakdown voltage.
As can be easily understood from the figure, unlike the above, the width and the impurity concentration of the base region 8 are substantially equal in the side direction of the emitter region 9 and the bottom direction of the emitter region 9, so that the flow of electrons in the side direction of the emitter region 9 is hindered. Without
Therefore, the present invention has a feature that is more suitable for a large current than a graft base structure.

In the present invention, the base region 8 and the emitter region 9 can be formed in the collector region 3 in a self-aligned manner by an ion implantation method using the electrode 7 as a mask by overlapping the electrode 7 with the emitter region 9. This facilitates fabrication and provides the advantage that the width of the surface of base region 8 between collector region 3 and emitter region 9 can be reduced. Of course, in this case, the surface of the base region 8 is covered with the electrode 7, but it is advantageous that the electrode 7 suppresses the spread of the depletion layer DL on the surface of the base region 8.

In the structure to which the present invention is applied as shown in FIG. 1 (b), a plurality of structures in which the emitter region 9 is formed in the base region 8 are provided, and the electrode 7 is commonly used as shown in FIG. Provided. By selecting a sufficiently small interval between the two base regions 8, the chip area is reduced as much as possible, and the depletion layers DL extending from both base regions 8 into the collector region 3 are joined to each other as shown in the figure.
By making the radius of curvature R larger than in the case of FIG. 1A, the withstand voltage value can be further improved.

〔Example〕

Hereinafter, an embodiment of the present invention will be specifically described with reference to FIG. 2 and FIG. In these figures, parts corresponding to those in FIGS. 4 and 5 are denoted by the same reference numerals. FIG. 2 shows an embodiment corresponding to the previous FIG. 1 (a), wherein FIG. 2 (a) shows a cross section and FIG. 2 (b) shows an upper surface.

In FIG. 2 (a), the integrated circuit device substrate 1 also has a p-type impurity concentration of about 10 ¹⁵ atoms / cm ³ , and the n-type buried layer 2 has a surface of 10 ¹⁸ atoms / cm 3. ^After being diffused in advance with a high impurity concentration of ³ or more, a high-resistance epitaxial layer 3 serving as an n-type collector region is formed, for example.
20μ for high withstand voltage with impurity concentration of 10 ¹⁴ atoms / cm ³
It is grown to a thickness of about m or more. As is customary, the p-type isolation layer 4 extends from the surface of the epitaxial layer 3 in FIG.
As shown in (1), the impurity is diffused at a high impurity concentration of 10 ¹⁹ atoms / cm ³ or more so as to incorporate a range in which a bipolar transistor is to be formed.

In the bipolar transistor, the epitaxial layer 3 surrounded by the separation layer 4 is formed as a collector region. For this purpose, first, the n-type low-resistance layer 5 for leading out the collector terminal C is formed of 10 ¹⁸ atoms / cm ³ or more. In this example, the light is diffused in a stripe pattern at a high impurity concentration as shown in FIG. The low resistance layer 5 is a so-called wall layer having a pattern surrounding the collector region 3 as necessary.

A silicon oxide film is usually used for the insulating film 11 below the electrode 7 and is formed on the surface of the central portion of the collector region 3 according to a desired withstand voltage value by, for example, a dry oxidation method, but with a thickness of at least 0.1 μm. In this example, prior to this, the periphery of the collector region 3 and the separation layer 4 are added.
A thick insulating film 12, which is a so-called LOCOS film, is formed to have a thickness of, for example, about 1 μm by means of a steam oxidation method or the like so as to continuously cover the surface.

The electrode 7 according to the present invention is preferably made of polycrystalline silicon similarly to the gate of the field effect transistor. The electrode 7 is grown by photo-etching, for example, to a thickness of about 0.5 μm by a conventional CVD method. In this example, as shown by hatching in FIG.
The electrode 7 in this example is formed on the thin insulating film 11 and the thick insulating film 12, as can be seen from FIG.
The thin insulating film 11 has a high effect of expanding the depletion layer DL along the surface of the collector region 3 under the electrode 7, and the effect is slightly reduced with the thick insulating film 12.

In this embodiment, both impurities for the base region 8 and the emitter region 9 are diffused by an ion implantation method using the electrode 7 as a mask, and the diffusion pattern is such that the base region 8 is square as shown in FIG. Reference numeral 9 denotes a square having a window in the center. P type base region 8 is 10 ¹⁷ atoms / c
to a depth of m ³ approximately impurity concentration, for example 3 [mu] m, the emitter region 9 of the n-type is 10 ²⁰ atoms / cm ³ about impurity concentration, for example 2
Each is built to a depth of μm. At this time, as usual, when boron is used as the p-type impurity and phosphorus is used as the n-type impurity, each impurity is thermally diffused individually at every ion implantation, and the diffusion rate of arsenic or the like is low instead of phosphorus. When impurities are used, they are simultaneously thermally diffused after ion implantation of both impurities.

As a result, the entire periphery of the base region 8 and a part of the outer periphery of the emitter region 9 are diffused so as to enter below the thin insulating film 11 as shown in the figure, so that the outer periphery of the emitter region 9 is separated from the collector region. The depletion layer DL is placed under the thin insulating film 11 so that the depletion layer DL easily spreads toward the third layer.

After the diffusion of the base region 8 and the emitter region 9, an upper insulating film 13, which is usually an oxide film, is entirely deposited, and electrode films 21 to 23 are provided in the windows opened at the key points as shown in the figure. The electrode film 21 for the collector terminal C is in conductive contact with the low resistance layer 5, the electrode film 22 for the emitter terminal E is in conductive contact with the emitter region 9, and the electrode film 23 for the base terminal B is in this example a window of the emitter region 9. The electrode 7 is brought into conductive contact with the central part of the base region 8, which corresponds to the part, and the electrode 7 is therefore placed at the same potential as the base region 8.

FIG. 2A shows the spread of the depletion layer DL in the off state of the bipolar transistor in this embodiment with hatching. The spread of the depletion layer DL
In the base region 8, it is suppressed as a whole by the electrode 7 under the thin insulating film 11, but is very small as a whole. Extends below the thin insulating film 11 beyond the thin insulating film 11 and serves to reduce local electric field concentration as described above.

Although the surface potential of the collector region 3 increases from the periphery of the base region 8 to the tip of the depletion layer DL, since the tip of the depletion layer DL goes under the thick insulating film 12, the electrode 7
Is assured by this thick insulating film 12. Also,
The spread of the depletion layer DL is not greatly promoted under the thick insulating film 12, and the so-called punch-through is prevented from being caused at its tip to reach, for example, the low resistance layer 5.

Further, in this embodiment, a single emitter region 9 is formed in the base region 8, but a plurality of emitter regions are formed concentrically, for example, so that the total peripheral length thereof is increased. It is possible to increase the current capacity without lowering the withstand voltage value.

FIG. 3 shows an embodiment corresponding to FIG. 1 (b), in which FIG. 3 (a) shows a cross section and FIG.
3 show the upper surfaces, respectively. It should be understood that the upper insulating film 13 and the electrode film in FIG. 2 are omitted in FIG. 3 in order to avoid unnecessarily complicating the figure.

In this embodiment, a plurality of base regions 8 and emitter regions 9 each having a stripe pattern are formed in the collector region 3 as a pair, and electrodes 7 having a stripe pattern are adjacent to each other. 9 is provided in common with the pair. Further, a graft region 6 is provided for resistance to both ends.

In FIG. 3 (a), the process is the same as in the previous embodiment until the low resistance layer 5 is diffused into the collector region 3.
According to the required withstand voltage value at an impurity concentration of, for example, 10 < ¹⁵ > to 10 < ¹⁶ > atoms / cm < ³ >, as shown in FIG. To a depth of 4 to 6 μm. Next, after covering the surface with a thin insulating film 11 and a thick insulating film 12, as in the previous embodiment, a plurality of electrodes 7 are provided mainly on the thin insulating film 11 in a stripe pattern. At this time, as can be seen from FIG. 7B, each electrode 7 is patterned so that the upper and lower ends of the electrode are above the graft region 6 or slightly project from it.

Also in this example, the p-type impurity in the leaves of the base region 8 and the n-type impurity for the emitter region 9 are introduced by an ion implantation method using the electrode 7 as a part of the mask, and are individually thermally diffused each time. At this time, the base region 8 is formed below the electrode 7 and is overlapped with the graft region 6 in the other portions. The emitter region 9 is formed in the base region 8 and, as can be seen from FIG. 3B, a part or most of the periphery thereof is sunk below the electrode 7.

As shown in FIG. 3 (b), the collector terminal C is formed from the low-resistance layer 5 connected to the collector region 3 via the buried layer 2, and the emitter terminal E is formed from a plurality of emitter regions 9 and a plurality of emitter regions 9 in this example. From the electrodes 7, the base terminals B are respectively taken from a plurality of base regions 8. Therefore, in this embodiment, the electrode 7 is placed at the same potential as the emitter region 9 having substantially the same potential as the base region. This is advantageous for always stabilizing the potential of the electrode 7 when the base terminal B can be at a floating potential during the operation of the transistor.

FIG. 7A shows the depletion layer DL when the transistor is turned off, with hatching. In this embodiment, the depletion layer DL is fused between the base regions 8 as shown in the drawing, and the depletion layer DL spreads from the end base region 8 into the graft region 6, so that a high breakdown voltage is obtained. Further, the layer peripheral length of the emitter region 9, that is, the total length of the corners at the bottom thereof is larger than in the previous example, so that a large current capacity can be obtained.

In the bipolar transistor according to the present embodiment configured as described above, for example, by forming a dozen pairs of base regions 8 and emitter regions 9 in a chip area of about 100 × 300 μm, a high withstand voltage of about 200 V and 100 mA This can have a large current capacity, and a current amplification factor of 100 to 150 can be obtained.

It should be noted that the graft region 6 in this embodiment can be replaced by an electrode 7. In this case, the electrode 7 is a single electrode having a shape in which a plurality of stripe-shaped electrodes are suspended between the opposite sides of the frame-shaped electrode, and the base region 8 and the emitter region 9 are formed from each window.

As can be seen from the above, the present invention is not limited to the embodiments described above, but can be implemented in various modes. For example, since it is sufficient to apply a potential substantially equal to that of the base region to the electrode, there is practically no significant difference when this is connected to either the base region or the emitter region. The electrodes are made of polycrystalline silicon as in the embodiment, which is advantageous when the bipolar transistor according to the present invention is built in a BiMOS circuit or the like.However, this is made of an appropriate metal film such as aluminum for an electrode film. There is no harm in configuring. In the embodiment, the electrode pattern, the type and thickness of the insulating film, the conductivity type of each region,
The patterns of the base region and the emitter region, the impurity concentration, the diffusion depth, and the like are merely examples, and should be appropriately selected according to the ratings and characteristics required for the bipolar transistor in practice. Further, as partially described in the examples, the structure according to the present invention is appropriately combined with the structure according to the related art such as the graft region, and part or all of the effects are effectively used within the gist of the present invention. Can be.

〔The invention's effect〕

As is apparent from the above description, in the present invention, a collector region of one conductivity type, an electrode formed in the collector region with an insulating film formed on the surface thereof, and masking the electrode in the collector region from the surface thereof A base region formed by diffusion of another conductivity type, and an emitter region formed by diffusion from one surface of the base region using the electrode as a mask, and a potential substantially equal to that of the base region in the electrode. The depletion layer is spread laterally from the periphery of the emitter region under the insulating film toward the collector region by the potential applied to this electrode, thereby reducing the electric field concentration generated at the bottom corner of the base region. By effectively relaxing, the withstand voltage value can be improved as compared with the related art. In addition, the expansion of the depletion layer does not hinder the emitter current path, and the width of the base region formed immediately below the electrode is narrow, so that current can flow from the side surface of the emitter region. The current capacity can be improved. Further, since the spread of the depletion layer can be accurately controlled by the pattern applied to the electrode, there is no need to take a margin in the pattern dimension, and the chip area can be reduced as compared with the conventional case.

For example, even in the simplest example shown in FIG. 2 having a single base region and emitter region, a high withstand voltage value of 180 V can be obtained, and the current capacity can be reduced by 20% compared to the conventional one with the same chip area.
The above can be improved.

According to the aspect in which a plurality of pairs of the base region and the emitter region are provided, and the common electrode is provided in the adjacent pair, the peripheral length of the emitter region is increased to increase the current capacity, and the breakdown voltage value is further increased. Can be improved.

For example, even when several pairs of a base region and an emitter region are provided as shown in FIG. 3, a high withstand voltage of about 200 V can be easily obtained, and the current capacity can be improved by about 50% with the same chip area as compared with the conventional case. be able to.

The present invention is applicable not only to bipolar transistors in general, but also to a BiMOS integrated circuit device, which is very advantageous, and is directly driven by a large-capacity load due to the above-described effects of high breakdown voltage, large current, and small size. And contribute to its further development and spread.

[Brief description of the drawings]

FIGS. 1 to 3 relate to the present invention, and FIGS. 1 (a) and (b) are cross-sectional views showing main parts of a basic structure of a bipolar transistor according to the present invention, and FIGS. 2 (a) and (b). 3 (a) and 3 (b) are a sectional view and a top view, respectively, showing different embodiments of the present invention. FIG. 4 et seq. Relate to the prior art, FIG. 4 is a sectional view of a conventional high breakdown voltage bipolar transistor, and FIG. 5 is a sectional view of a conventional large current bipolar transistor. In the figure, 1: semiconductor substrate for integrated circuit device, 2: buried layer, 3: collector region or epitaxial layer, 4: isolation layer, 5: low resistance layer for collector terminal, 6: graft region, 7: electrode, 8 : Base area,
9: emitter region, 10: insulating film, 11: thin insulating film, 12: thick insulating film, 13: upper insulating film, 21: electrode film for collector terminal, 2
2: Electrode film for emitter terminal, 23: Electrode film for base terminal, B:
Base terminal, C: collector terminal, DL: depletion layer, E: emitter terminal, e: electron, R: radius of curvature of depletion layer, r: radius of curvature of bottom corner of base region.

Claims (1)

(57) [Claims] 1. A collector region of one conductivity type, and an electrode formed on the surface of the collector region via an insulating film,
A collector region includes a base region of the other conductivity type and an emitter region of one conductivity type, which are formed in a self-aligned manner from the surface thereof in a self-aligned manner by using the electrode as a mask so that a peripheral portion of the electrode is sunk under the electrode. The electrode faces the continuous collector region, the base region, and a region including at least the periphery of the emitter region on the surface of the emitter region via an insulating film, and applies a potential substantially equal to that of the base region to the electrode. A bipolar transistor, characterized in that: