JPH0513800A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reduce an irregularity in the characteristics of a signal processing transistor by a method wherein the signal processing transistor is formed on the fifth semiconductor layer which is of the first conductivity type and which has been grown epitaxially. CONSTITUTION:A photodiode part A is composed of the following: a P-type anode diffusion layer (PA) 5 formed on an N-type high-resistivity semiconductor substrate (NB) 1 in the prescribed region of an N-type epitaxial layer (NE) 4 so as to pass the NE 4; an N-type buried diffusion layer (ND) 3 formed so as to be buried in the NB 1 by keeping a prescribed interval from the PA 5; and an N-type cathode compensation diffusion layer 6 formed inside the NE 4 on the ND 3. An NPN transistor part B is composed of the following: an NE 4 formed on a P-type buried diffusion layer 2 and on an ND 3a; a P-type base diffusion layer (PB) 7 formed in a prescribed region on the main surface of the NE 4; an N-type emitter diffusion layer 8 formed in a prescribed region on the surface of the PB 7; and an N-type collector compensation diffusion layer 6a formed on the ND 3a by keeping a prescribed interval from the PB 7.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device,
In particular, the present invention relates to a semiconductor device having a light-receiving element formation region and a signal processing circuit formation region which are adjacent to each other on a first conductivity type high resistivity semiconductor substrate.

[0002]

2. Description of the Related Art Conventionally, a circuit built-in light receiving element has been known as one of light receiving elements such as an optical sensor and a photocoupler.

FIG. 5 is a sectional view showing a conventional general photodetector with a built-in circuit. Referring to FIG. 5, a conventional general photodetector with a built-in circuit has a photodiode section (A) which is a region where a photodiode, which is a photodetector, is formed.
And an NPN transistor portion (B) which is a region where an NPN transistor which is a signal processing circuit element is formed. The photodiode part (A) and the NPN transistor part (B) are separated by a P-type separation diffusion layer 5a formed on the semiconductor substrate 11.

The photodiode section (A) includes an N-type buried diffusion layer 3 buried in a P-type semiconductor substrate 11, an N-type epitaxial layer 4 grown on the N-type buried diffusion layer 3.
A P-type diffusion layer 7a formed in a predetermined region on the surface of the N-type epitaxial layer 4, and an N-type buried diffusion layer on the surface of the N-type epitaxial layer 4 at a predetermined distance from the P-type diffusion layer 7a. 3 and an N-type cathode compensation diffusion layer 6 formed so as to reach 3.

The P-type diffusion layer 7a corresponds to the anode of the photodiode, and the N-type cathode compensation diffusion layer 6 corresponds to the cathode of the photodiode.

The NPN transistor portion (B) has an N-type buried diffusion layer 3a formed so as to be buried in the P-type semiconductor substrate 11, and an N-type epitaxial layer 4a grown on the N-type buried diffusion layer 3a. A P-type base diffusion layer 7 formed in a predetermined region on the main surface of the N-type epitaxial layer 4a, and P
N type emitter diffusion layer 8 formed in a predetermined region on the surface of type base diffusion layer 7 and the main surface of N type epitaxial layer 4a are separated from P type base diffusion layer 7 by a predetermined distance.
And an N-type collector compensation diffusion layer 6a formed so as to reach the type buried diffusion layer 3a.

The N-type emitter diffusion layer 8, the P-type base diffusion layer 7 and the N-type collector compensation diffusion layer 6a form an NPN.
A transistor is constructed.

[0008]

A conventional general photodetector with a built-in circuit is constructed as described above.

By the way, recently, speeding up of data transmission, S
Due to demands such as improvement in / N ratio, it is desired to increase the sensitivity and response speed of the light receiving element with a built-in circuit.

However, in the conventional general photodetector with a built-in circuit shown in FIG. 5, it is difficult to realize high photosensitivity and high response speed at the same time for the following reasons. Hereinafter, the reason will be described in detail.

In the conventional photodetector with a built-in circuit shown in FIG. 5, the N-type epitaxial layer 4 of the photodiode section (A) is designed to have a high photosensitivity in accordance with the wavelength of light used for signals. It is necessary to make the thickness sufficiently thick.

However, the N type epitaxial layer 4 of the photodiode section (A) and the N type epitaxial layer 4a of the NPN transistor section (B) are formed by the same manufacturing process. Therefore, N of the photodiode section (A)
If the thickness of the epitaxial layer 4 is increased, the NPN
The N-type epitaxial layer 4a of the transistor portion (B) is also formed thick.

However, when the thickness of the N-type epitaxial layer 4a of the NPN transistor portion (B) becomes thicker, the resistance component becomes longer due to the thickening, and the collector resistance of the NPN transistor increases. As a result, there is a problem that it is difficult to increase the response speed of the NPN transistor.

The specific resistance of the N type epitaxial layer 4 of the photodiode portion (A) is about several Ω · cm because it is formed in the same step as the N type epitaxial layer 4a of the NPN transistor portion (B). And lower. For this reason, there is a disadvantage that a portion that does not become a depletion layer remains in the N-type epitaxial layer 4 of the photodiode part (A) to be considerably thick. Since no electric field is applied to the portion that does not become the depletion layer, the generated photocarriers travel by diffusion. The time that the photo carriers travel by diffusion is longer than the time that the photo carriers travel by the electric field. As a result, there is a problem that it is difficult to increase the response speed.

By the way, in order to increase the response speed of the light receiving element with a built-in circuit, it is effective to reduce the junction capacitance of the photodiode section (A). In order to reduce the junction capacitance, it is necessary to increase the specific resistance of the N-type epitaxial layer 4 of the photodiode part (A).

However, if the N-type epitaxial layer 4 of the photodiode part (A) is made to have a high specific resistance, the specific resistance of the N-type epitaxial layer 4a of the NPN transistor part (B) becomes high. When the specific resistance of the N-type epitaxial layer 4a of the NPN transistor section (B) becomes high, the collector resistance of the NPN transistor increases, which is a disadvantage. As a result, there is a problem that it is difficult to increase the response speed.

That is, in order to achieve both high photosensitivity of the light receiving element with a built-in circuit and high response speed, the N-type epitaxial layer 4 of the photodiode section (A) has a high specific resistance and a large thickness. Is required.

However, in order to achieve high photosensitivity,
When the thickness of the N-type epitaxial layer 4 of the photodiode part (A) is increased, the collector resistance of the NPN transistor increases and the part of the N-type epitaxial layer 4 of the photodiode part (A) that does not become a depletion layer as described above. And cause an increase in. As a result, it has been difficult to increase the response speed of the NPN transistor.

If the N-type epitaxial layer 4 is made to have a high specific resistance in order to reduce the junction capacitance of the photodiode portion (A) in order to achieve a high response speed, N
N-type epitaxial layer 4a of PN transistor part (B)
Also has a high specific resistance. As a result, there is a problem that the collector resistance of the NPN transistor increases and the response speed cannot be increased.

Therefore, from the above, the N-type epitaxial layer 4a of the NPN transistor portion (B) needs to have a low specific resistance and a thin thickness in order to achieve a high response speed.

Various proposals have been made in order to solve the above-mentioned problems of the conventional light receiving element with a built-in circuit.

These are disclosed, for example, in Japanese Patent Laid-Open No. 63-122.
It is disclosed in Japanese Patent No. FIG. 6 is a cross-sectional view showing the disclosed conventional improved light receiving element with a built-in circuit.

Referring to FIG. 6, a conventional improved light receiving element with a built-in circuit is similar to the conventional light receiving element with a built-in circuit shown in FIG. And B) are formed adjacent to each other.

The photodiode portion (A) is composed of an N-type epitaxial layer 9 having a high specific resistance of several tens to several hundreds Ω · cm grown on a high-specific resistance N-type semiconductor substrate 1, and an N-type epitaxial layer. The P-type diffusion layer 7a formed in a predetermined region on the surface of the N 9 and the N-type semiconductor substrate 1 are formed so as to be embedded in the N-type semiconductor substrate 1 with a predetermined space therebetween, and N for extracting a cathode electrode.
Type buried diffusion layer 3 and N formed on the N type buried diffusion layer 3
Type cathode compensation diffusion layer 6. In addition, i described in the portions corresponding to the N-type semiconductor substrate 1 and the N-type epitaxial layer 9 means that it is close to an intrinsic semiconductor.

An N-type semiconductor substrate 1 having a high specific resistance,
The N-type epitaxial layer 9 and the P-type diffusion layer 7a form a photodiode.

The NPN transistor portion (B) has a P-type buried diffusion layer 2 embedded on an N-type semiconductor substrate 1 having a high specific resistance.
And N formed in a predetermined region on the surface of the P type buried diffusion layer 2.
Type buried diffusion layer 3a and an N type epitaxial layer 9a grown on the N type buried diffusion layer 3a and having a high specific resistance of several tens to several hundreds Ω · cm (compensated by an N type diffusion layer 10 described later). 6 is not shown in FIG. 6), the N-type diffusion layer 10 formed so as to reach the N-type buried diffusion layer 3a from the surface of the N-type epitaxial layer 9a, and the N-type diffusion layer 1
P type base diffusion layer 7 formed in a predetermined area on the surface of
, An N-type emitter diffusion layer 8 formed in a predetermined region on the surface of the P-type base diffusion layer 7, and an N on the N-type buried diffusion layer 3a.
The N type collector compensation diffusion layer 6a is formed so as to be adjacent to the type diffusion layer 10.

The photodiode section (A) and the NPN transistor section (B) are separated by a P-type separation diffusion layer 5a.

In such a conventional improved light receiving element with a built-in circuit, the photodiode section (A) has a high specific resistance N.
The thick semiconductor substrate 1 and the N-type epitaxial layer 9 having a high specific resistance realize a thick N-type semiconductor layer having a high specific resistance. Further, the NPN transistor part (B) includes an N-type epitaxial layer 9 having a high specific resistance compensated by the N-type diffusion layer 10.
High-speed response is realized by setting a (not shown) to an optimum thickness and specific resistance.

However, the conventional improved photodetector with a built-in circuit shown in FIG. 6 has the following problems.

That is, in this improved example, the NPN transistor constituted by the N-type emitter diffusion layer 8, the P-type base diffusion layer 7 and the N-type collector compensation diffusion layer 6a is formed in the N-type diffusion layer 10. It Therefore, variations in the manufacturing process of the N-type diffusion layer 10 lead to variations in the characteristics of the NPN transistor. That is, in this improved example, the impurity concentration profile of the N-type diffusion layer 10 needs to be flat in the depth direction in order to reduce the characteristic variation of the NPN transistor. In order to make the impurity concentration profile of the N-type diffusion layer 10 flat in the depth direction, it is necessary to perform high-temperature heat treatment for a long time. When the heat treatment is applied for a long time in this way, the P-type isolation diffusion layer 5a expands in the lateral direction, and as a result, there is a problem that the size of the NPN transistor cannot be reduced. This problem becomes more remarkable as the thickness of the N-type high specific resistance epitaxial layer 9 becomes thinner. Therefore, in this improved example, N
There has been a problem that it is not possible to achieve high integration and high speed of the signal processing circuit which requires the thinning of the high resistivity epitaxial layer 9. Further, in this improved example, the number of steps for forming the P-type buried diffusion layer 2 and the N-type diffusion layer 10 is increased as compared with the conventional general circuit built-in light receiving element shown in FIG. Therefore, there are problems that the manufacturing process is complicated and the manufacturing cost is increased.

The present invention has been made in order to solve the above problems, and it is possible to reduce the characteristic variation of the signal processing transistor (NPN transistor) as compared with the conventional one and to simplify the manufacturing process. It is an object of the present invention to provide a new semiconductor device.

[0032]

According to another aspect of the present invention, there is provided a semiconductor device having a light receiving element forming region and a signal processing circuit forming region which are adjacent to each other on a first conductivity type high resistivity semiconductor substrate. A first semiconductor layer having a low specific resistance and a first conductivity type formed in a light receiving element formation region on the high specific resistance semiconductor substrate, and formed on the high specific resistance semiconductor substrate so as to penetrate the first semiconductor layer Second having a second conductivity type
Semiconductor layer, a third semiconductor layer having a second conductivity type formed in the signal processing circuit formation region on the high-resistivity semiconductor substrate, and a first conductivity type formed so as to be embedded in the third semiconductor layer. A fourth semiconductor layer, a fifth semiconductor layer formed on the fourth semiconductor layer and having a first conductivity type and epitaxially grown, and a signal processing transistor formed on the fifth semiconductor layer. There is.

[0033]

In the semiconductor device according to the present invention, since the signal processing transistor is formed in the epitaxially grown fifth semiconductor layer having the first conductivity type, the signal processing transistor is formed in the impurity diffusion layer as in the conventional case. Therefore, various inconveniences, which have been problems in the past, can be solved.

[0034]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a sectional view showing a light receiving element with a built-in circuit according to an embodiment of the present invention. Referring to FIG. 1, the light receiving element with a built-in circuit according to this embodiment has a photodiode section (A).
And an NPN transistor section (B).

The photodiode section (A) penetrates the N-type epitaxial layer 4 in a predetermined region of the N-type epitaxial layer 4 grown by stacking on the N-type high resistivity semiconductor substrate 1. Then, the P-type anode diffusion layer 5 formed on the N-type high specific resistance semiconductor substrate 1 and the N type high specific resistance semiconductor substrate 1 separated from the P type anode diffusion layer 5 by a predetermined distance are formed. N-type buried diffusion layer 3
And an N-type cathode compensation diffusion layer 6 formed in the N-type epitaxial layer 4 on the N-type buried diffusion layer 3.

The NPN transistor portion (B) has a P-type buried diffusion layer 2 formed so as to be embedded in the N-type high specific resistance semiconductor substrate 1, and an N formed on the surface of the P-type buried diffusion layer 2.
A type buried diffusion layer 3a, an N type epitaxial layer 4 formed on the P type buried diffusion layer 2 and the N type buried diffusion layer 3a,
A P-type base diffusion layer 7 formed in a predetermined region on the main surface of the N-type epitaxial layer 4, an N-type emitter diffusion layer 8 formed in a predetermined region on the surface of the P-type base diffusion layer 7, and P
And an N-type collector compensation diffusion layer 6a formed on the N-type buried diffusion layer 3a at a predetermined distance from the type base diffusion layer 7.

The photodiode section (A) and the NPN transistor section (B) are separated by a P-type separation diffusion layer 5a.

In this embodiment, the NPN transistor including the N-type emitter diffusion layer 8, the P-type base diffusion layer 7 and the N-type collector compensation diffusion layer 6a is thus formed in the N-type epitaxial layer 4. As a result, it is not necessary to form the N-type diffusion layer 10 as in the conventional improved example shown in FIG. 6, and various inconveniences associated with the formation of the N-type diffusion layer 10 can be eliminated. That is, as in the conventional improvement example, N
Due to the dispersion of the diffusion profile of the type diffusion layer 10, the depth of the P-type base diffusion layer 7 does not vary. As a result, it is possible to solve the problem that the characteristics of the NPN transistor vary. Further, in this embodiment, since heat treatment at high temperature for a long time for flattening the impurity profile of the N-type diffusion layer 10 is not required, unlike the conventional improvement example, the P-type isolation diffusion layer is formed during the heat treatment. It is possible to eliminate the inconvenience that 5a and the like spread. As a result, it is possible to solve the problem that the size of the NPN transistor becomes large and it is difficult to achieve high integration and high speed of the signal processing circuit unit as in the conventional improved example.

2 to 4 are cross-sectional views for explaining the manufacturing process (first step to third step) of the light receiving element with a built-in circuit shown in FIG. With reference to FIG. 1 and FIG. 2 to FIG. 4, a manufacturing process of the light receiving element with a built-in circuit of this embodiment will be described.

First, as shown in FIG. 2, a P type buried diffusion layer 2 is formed in a signal processing circuit element forming region on an N type high resistivity semiconductor substrate 1. An N type buried diffusion layer 3a is formed in a predetermined region on the surface of the P type buried diffusion layer 2. At the same time,
On the N-type high specific resistance semiconductor substrate 1 in the region where the photodiode is to be formed, the N-type buried diffusion layers 3 are formed at a predetermined interval. The N-type buried diffusion layer 3 becomes a cathode electrode extraction region.

Next, as shown in FIG. 3, several Ωc over the entire surface
The N-type epitaxial layer 4 of about m is grown. At this time, the P-type buried diffusion layer 2 and the N-type buried diffusion layers 3, 3a
Respectively diffuse upwards.

Next, as shown in FIG. 4, a P-type anode diffusion layer 5 and a P-type isolation diffusion layer 5a forming a photodiode are formed in a predetermined region on the N-type epitaxial layer 4 by diffusion. Note that it is not always necessary to perform the diffusion at the same time, and it may be performed separately. In addition, the P-type isolation diffusion layer 5a or the P-type anode diffusion layer 5
Alternatively, the diffusion may be performed by combining the diffusion layer previously embedded in the N-type high resistivity semiconductor substrate 1 and the diffusion layer diffusing from the surface of the N-type epitaxial layer 4.

After such steps, the structure shown in FIG. 1 is obtained through the same steps as the manufacturing steps of the conventional photodetector with a built-in circuit shown in FIG.

As described above, in the light receiving element with a built-in circuit of the present embodiment, since the NPN transistor is formed in the N type epitaxial layer 4, the N type impurity diffusion is performed as compared with the conventional improved example shown in FIG. The step of forming layer 10 is omitted. Therefore, the manufacturing process can be simplified and the manufacturing cost can be reduced.

The N-type epitaxial layer 4 of this embodiment is also used.
The thickness of can be set to an optimum value for the NPN transistor. As a result, the size of the NPN transistor can be made equal to that of a normal highly integrated and high speed bipolar IC. This makes it possible to achieve high integration and high speed of the signal processing circuit.

Further, in the light receiving element with a built-in circuit of this embodiment,
The P-type anode diffusion layer 5 of the photodiode part (A) is
It penetrates through the low resistivity epitaxial layer 9 and reaches the N-type high resistivity semiconductor substrate 1. This is for the following reason. That is, if the P-type anode diffusion layer 5 does not reach the N-type high resistivity semiconductor substrate 1, the depletion layer spreading in the photodiode section (A) stops in the N-type epitaxial layer 4 having a low resistivity. Because it will be.
In such a case, since the photodiode junction capacitance is increased several times, the response speed of the photodiode may be extremely slow. Therefore, in this embodiment, the P-type anode diffusion layer 5 penetrates the low-resistivity N-type epitaxial layer 4 and reaches the N-type high-resistivity semiconductor substrate 1.

It is the response speed of the photodiode that the photodetector with a built-in circuit shown in FIG. 1 may be inferior to the conventional improved photodetector with a built-in circuit shown in FIG. In the present embodiment, it will be described below that there is no problem with this response speed.

There are the following three factors (elements) that govern the response speed of the photodiode.

That is, one is a diffusion time constant required for the photocarriers generated outside the depletion layer to reach the depletion layer by diffusion, and the other is a diffusion time constant required for the carriers to travel in the depletion layer. It is a drift time constant, and the other is a CR time constant due to the junction capacitance.

In the photodiode section (A) of this embodiment, the N-type high specific resistance semiconductor substrate 1 is the N type high specific resistance epitaxial layer 9 and the N type high specific resistance semiconductor substrate 1 shown in FIG.
Corresponds to the combined part. As a result, the widths of the depletion layer spread at the same reverse bias voltage become equal. Therefore, among the above-mentioned factors, the diffusion time constant and the drift time constant are the same as those of this embodiment and the conventional improved example shown in FIG.

Regarding the CR time constant among the above-mentioned factors, as shown below, the difference between this embodiment and the conventional improved example shown in FIG. 6 is not so large and is practically no problem. Is.

That is, the junction capacitance between the N-type epitaxial layer 4 and the P-type anode diffusion layer 5 of this embodiment is shown in FIG.
It becomes larger than the junction capacitance between the N-type high specific resistance epitaxial layer 9 and the P-type diffusion layer 7a of the conventional improved example shown in FIG. For this reason, the CR time constant of the present embodiment is slightly larger than the CR time constant of the conventional improved example shown in FIG.

However, the junction area between the N-type epitaxial layer 4 and the P-type anode diffusion layer 5 of this embodiment is significantly smaller than the junction area of the entire photodiode. Therefore, the difference between the junction capacitance of the structure of the present embodiment and the junction capacitance of the conventional improved example shown in FIG. 6 is not so large. Therefore, the difference between the CR time constants is also within the range of practically no problem.

The junction capacitance will be specifically examined below. For example, the size of the photodiode is 500μ
m × 500 μm, N-type high resistivity epitaxial layer 9 is 1
00 Ω · cm, 2 μm, N type epitaxial layer 4 is 5 Ω
Cm, 2 μm, the specific resistance of the N-type high specific resistance semiconductor substrate 1 is 100 Ω · cm, and the depth of the P-type (anode) diffusion layer is 1 μm in the conventional P-type diffusion layer 7a shown in FIG. ，
In the P-type anode diffusion layer 5 of this embodiment shown in FIG.
5 μm.

When the junction capacitances of the photodiodes are compared under the above conditions, the following results are obtained. (Note that the reverse bias is 3 V.) The junction capacitance of the photodiode of this embodiment shown in FIG.
F, and the junction capacitance of the conventional improved photodiode shown in FIG. 6 was 2.91 pF.

That is, under this condition, the junction capacitance of the photodiode of this embodiment shown in FIG. 1 is higher than the junction capacitance of the photodiode of the conventional improved example shown in FIG. 6 by about 8%. .. However, as the characteristics of the photodiode, the above-mentioned photocarrier diffusion time constant is often more dominant than the CR time constant. Therefore, 8
The increase in the junction capacitance of the photodiode of about 10% does not pose a problem.

As described above, in the present embodiment, the response speed is considered to be equivalent to the structure of the conventional improved example shown in FIG.

[0059]

As described above, according to the present invention, the first
By forming a signal processing transistor on the epitaxially grown fifth semiconductor layer having a conductivity type,
It is not necessary to form the signal processing transistor in the impurity diffusion layer as in the conventional case. As a result, it is possible to reduce variations in the characteristics of the signal processing transistor (NPN transistor) as compared with the related art and to simplify the manufacturing process.

[Brief description of drawings]

FIG. 1 is a sectional view showing a light receiving element with a built-in circuit according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view for explaining the first step of the manufacturing process of the light-receiving element with built-in circuit shown in FIG.

FIG. 3 is a cross-sectional view for explaining a second step of the manufacturing process for the light-receiving element with a built-in circuit shown in FIG.

FIG. 4 is a cross-sectional view for explaining a third step of the manufacturing process of the light-receiving element with built-in circuit shown in FIG.

FIG. 5 is a sectional view showing a conventional general photodetector with a built-in circuit.

FIG. 6 is a cross-sectional view showing a conventional improved light receiving element with a built-in circuit.

[Explanation of symbols]

 1: N type high resistivity semiconductor substrate 2: P type buried diffusion layer 3, 3a: N type buried diffusion layer 4: N type epitaxial layer 5: P type anode diffusion layer 5a: P type separation diffusion layer 6: N Type cathode compensation diffusion layer 6a: N type collector compensation diffusion layer 7: P type base diffusion layer 8: N type emitter diffusion layer In each figure, the same reference numerals indicate the same or corresponding portions.

Claims (1)

Claim: What is claimed is: 1. A high conductivity semiconductor substrate of the first conductivity type,
A semiconductor device having a light receiving element forming region and a signal processing circuit forming region which are adjacent to each other, wherein the semiconductor device is formed in the light receiving element forming region on the high resistivity semiconductor substrate, and has a low specific resistance and a first conductivity type. Semiconductor layer, a second semiconductor layer having a second conductivity type and formed on the high-resistivity semiconductor substrate so as to penetrate the first semiconductor layer, and a signal processing circuit formation region on the semiconductor substrate. Formed in
A third semiconductor layer having a second conductivity type, a fourth semiconductor layer having a first conductivity type formed so as to be embedded in the third semiconductor layer, and formed on the fourth semiconductor layer, A semiconductor device comprising: an epitaxially grown fifth semiconductor layer having a first conductivity type; and a signal processing transistor formed in the fifth semiconductor layer.