JP2700356B2 - Light receiving element - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure for increasing the response speed of a light receiving element.

[0002]

2. Description of the Related Art Light receiving elements are widely used in photocouplers, optical fibers, and the like, and various structures have been proposed to increase the response speed.

FIG. 9 is a schematic sectional view of an example of a pin photodiode. Such an apparatus is created by the following steps. First, on the N-type low resistivity semiconductor substrate 1,
For example, an N-type high resistivity epitaxial layer 6 of about 100 ohm cm is laminated. Next, a P-type diffusion layer 3 is formed on the surface of the N-type high resistivity epitaxial layer 6 as an anode. If the light receiving element is used with a reverse bias of 5 volts, the width of the depletion layer on the cathode side is about 12 microns, so that the thickness of the N-type high resistivity epitaxial layer 6 is Is set so that the distance from the bottom surface to the surface of the N-type low resistivity semiconductor substrate 1 is about 12 microns. This surface is covered with a surface protection film 4 such as silicon oxide. A hole is formed in a desired place of the surface protective film 4 and an anode terminal 5 is provided. Although not shown, the cathode terminal is provided on the back surface of the N-type low resistivity semiconductor substrate 1.

As described above, a high-speed response is devised by using the N-type high-resistivity epitaxial layer 6 as a light receiving portion.

[0005]

However, in the light-receiving element having the above-described structure, since the high resistivity portion of the N-type layer serving as the cathode is formed by the epitaxial layer, it is difficult to further increase the resistivity. , 300 ohm cm is the limit, and the junction capacitance cannot be sufficiently reduced.
For this reason, the CR time constant cannot be made sufficiently small, which hinders speeding up. In addition, by a high-temperature heat treatment such as epitaxial growth, the N-type low resistivity semiconductor substrate 1 having a high impurity concentration is
Since the N-type impurity climbs into the N-type high-resistivity epitaxial layer 6, carriers generated in the crest portion that is not depleted reach the depletion layer by diffusion.
Prevents faster response speed.

An object of the present invention is to increase the response speed of a light receiving element, excluding the above-mentioned disadvantages.

[0007]

According to the present invention, for example, an N-type high-resistivity semiconductor substrate is bonded to the surface of an N-type low-resistivity semiconductor substrate by a substrate bonding method. The thickness of the semiconductor substrate is such that the thickness from the bottom surface of the anode formed on the surface to the surface of the N-type low resistivity semiconductor substrate is equal to the width of the depletion layer spread by the reverse bias applied to the light receiving element. It was set to become.

[0008]

According to the present invention having the above structure, a high specific resistance semiconductor substrate is used for the high specific resistance portion of the cathode, so that it cannot be obtained by epitaxial growth.
A high resistivity layer of about 000 ohm cm can be obtained, the junction capacitance can be sufficiently reduced, and the CR time constant can be reduced. In addition, since the high-resistivity substrate and the low-resistivity semiconductor substrate are bonded to each other by the substrate bonding method, the rise of impurities from the low-resistivity semiconductor substrate to the high-resistivity semiconductor substrate is suppressed,
The impurity concentration profile can be kept steep. This makes it possible to sharpen the impurity concentration profile of a region other than the depletion layer that is spread by the reverse bias applied to the light receiving element, so that carriers generated outside the depletion layer have a short lifetime and do not contribute to the photocurrent.

By adopting such a structure, a diffusion current component which hinders an increase in response speed does not contribute to
An excellent light receiving element having a small time constant can be obtained.

[0010]

FIG. 1 is a schematic sectional view showing the structure of an embodiment of the present invention. The difference from the conventional example of FIG. 9 is that the N-type high-resistivity semiconductor substrate 2 is used instead of the N-type high-resistivity epitaxial layer 6 and is polished to a desired thickness.
9 are denoted by the same reference numerals. This device is manufactured in a process as shown in the schematic sectional views of FIGS.

First, as shown in FIG. 2, assuming that the first conductivity type is N-type, an N-type high-resistivity semiconductor substrate 2 of about 1000 ohm cm is provided on the surface of the N-type low-resistivity semiconductor substrate 1. Are bonded in the direction of the arrow by a wafer bonding method.

Next, as shown in FIG. 3, the N-type high resistivity semiconductor substrate 2 is polished to a desired thickness. If the light receiving element is used with a reverse bias of 5 volts, the width of the depletion layer on the cathode side is about 35 microns, so that the thickness of the N-type high-resistivity semiconductor substrate is P The distance from the bottom of the type diffusion layer 3 to the surface of the N-type low-resistivity semiconductor substrate 1 is set to about 35 microns.

Next, as shown in FIG. 1, a P-type diffusion layer 3 of the second conductivity type serving as an anode is provided on the surface of an N-type high resistivity semiconductor substrate 2. These surfaces are covered with a surface protective film 4, holes are formed at desired locations, and anode terminals 5 are provided. Although not shown, the cathode terminal is provided on the back surface of the N-type low resistivity semiconductor substrate 1.

In the above embodiment, the structure in which only a single light receiving element is formed has been described. However, the present invention is also applicable to a structure in which the light receiving element and the signal processing circuit are formed on the same chip.

FIG. 4 is a schematic sectional view showing one embodiment of a structure in which a light receiving element and a signal processing circuit are formed on the same chip. 1 are represented by the same reference numerals. A light receiving element section 20 is formed on the left side of the figure, and a signal processing circuit section 21 is formed on the right side.

This device is manufactured by the steps shown in the schematic sectional views of FIGS. First, as shown in FIG. 5, a P-type buried diffusion layer 7 is formed in a region for a signal processing circuit of an N-type high resistivity semiconductor substrate 2 of about 1000 ohm cm.
To form Next, this N-type high resistivity semiconductor substrate 2 is
It is bonded to the surface of the N-type low resistivity semiconductor substrate 1 in the direction of the arrow by a wafer bonding method. Here, the P-type buried diffusion layer 7
Is for electrically separating the light receiving element from the signal processing circuit.

Next, as shown in FIG. 6, the N-type high resistivity semiconductor substrate 2 is polished to a desired thickness. When the light receiving element is used with a reverse bias of 5 volts, the width of the depletion layer on the cathode side is about 35 μm as in the above embodiment, so that the thickness of the N-type high resistivity semiconductor substrate 2 will be N from the bottom of the P-type diffusion layer 11 serving as an anode formed in the process.
It is set to be about 35 microns up to the surface of the mold low resistivity semiconductor substrate 1.

Next, as shown in FIG. 7, an N-type buried diffusion layer 8 is formed only in a region where a signal processing circuit is to be formed, and an N-type epitaxial layer having an impurity concentration suitable for the signal processing circuit is formed on the entire surface thereof. 9 are stacked.

Next, as shown in FIG. 8, a P-type separation / diffusion layer 10 is formed on the peripheral portion of the P-type buried diffusion layer 7 to separate each element. At the same time, a P-type diffusion layer 11 serving as an anode is formed on the surface of the light receiving element.

Next, as shown in FIG. 4, a P-type base diffusion layer 12, an N-type collector diffusion layer 14, and an N-type emitter A diffusion layer 13 is formed. By these, NPN
A transistor is configured. These surfaces are covered with a surface protective film 4, and holes are formed at desired locations on the surface protective film 4, and the anode terminal 5, the base terminal 15, and the collector terminal 1 are formed.
7, an emitter terminal 16 and the like are provided. Although not shown, the cathode terminal is provided on the back surface of the N-type low resistivity semiconductor substrate 1.

In the present embodiment, the cathode terminal is provided on the back surface. However, the cathode terminal is formed by sequentially performing appropriate diffusion such as an N-type buried diffusion layer at an appropriate position of the light receiving element 20. It can also be provided on the surface. Further, the P-type buried diffusion layer 7 is formed before the N-type low-resistivity semiconductor substrate 1 and the N-type high-resistivity semiconductor substrate 2 are bonded, but after the N-type high-resistivity semiconductor substrate 2 is polished. You can do it.

The above P-type semiconductor can be replaced with an N-type semiconductor.

[0023]

According to the present invention, since a high resistivity semiconductor substrate having a low impurity concentration is used as the i-layer of the pin photodiode, the resistivity of the i-layer cannot be increased by the epitaxial layer.
The resistivity can be as high as 00 ohm cm or more, the width of the depletion layer on the cathode side of the light receiving element can be increased, and the junction capacitance can be reduced, so that the CR time constant can be reduced.

Further, by using the bonding technique, the n-type impurity from the n-type low-resistivity semiconductor substrate 1 is prevented from rising, and the impurity concentration profile outside the depletion layer spreading to the cathode side can be steeply maintained. The lifetime of carriers generated outside the layer is shortened, the diffusion component reaching the depletion layer can be greatly reduced, and the light-receiving element can operate at high speed.

In a structure in which the light receiving element and the signal processing circuit are formed on the same chip, the heat treatment for forming the P-type buried diffusion layer 7 can be performed before bonding the wafers. It is possible to suppress the n-type impurity from rising from 1. Therefore, a high-speed operation of the light receiving element is possible.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view of one embodiment of the present invention.

FIG. 2 is a schematic sectional view of a process of the present invention.

FIG. 3 is a schematic sectional view of a process of the present invention.

FIG. 4 is a schematic sectional view of another embodiment of the present invention.

FIG. 5 is a schematic sectional view showing a step of FIG. 4;

FIG. 6 is a schematic sectional view showing a step of FIG. 4;

FIG. 7 is a schematic sectional view showing the step of FIG. 4;

FIG. 8 is a schematic sectional view showing the step of FIG. 4;

FIG. 9 is a schematic cross-sectional view of an example of the related art.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 N-type low resistivity semiconductor substrate 2 N-type high resistivity semiconductor substrate 3 P-type diffusion layer 4 surface protection film 6 N-type high resistivity epitaxial layer 7 P-type buried diffusion layer 8 N-type buried diffusion layer 9 N-type Epitaxial layer 10 P-type isolation diffusion layer 11 P-type diffusion layer 12 Base diffusion layer 13 Emitter diffusion layer 14 Collector diffusion layer 15 Base terminal 16 Emitter terminal 17 Collector terminal

Claims (1)

(57) [Claims] 1. A low-resistance semiconductor substrate of a first conductivity type,
A high-resistivity semiconductor substrate of the same conductivity type bonded thereto; a second-conductivity-type diffusion layer formed on the surface of the high-resistivity semiconductor substrate; A light receiving element wherein the thickness up to the surface of the low resistivity semiconductor substrate is equal to the width of the depletion layer at the time of reverse bias.