JPH02196463A - Photodetector with built-in circuit - Google Patents

Abstract

PURPOSE:To obtain a photodetector built in circuit having sensitivity and speed which are superior than those of conventional photodetectors by causing a photodetector to be equipped with upper and lower epitaxial layers and a circuit element part to be equipped with the upper and lower epitaxial layers; besides, a buried layer to be provided between the upper and lower epitaxial layers. CONSTITUTION:This photodetector is composed of a photodetector part and a circuit element part which are surrounded with the second conductivity type buried layers 2 and 3 and diffusion layers 5, 6, and 10 that are formed on the surface of the first conductivity type semiconductor substrate 1. The photodetector part is equipped with the first conductivity type upper eqitaxial layer 9 and lower epitaxial layer 4 and the circuit element part is equipped with the first conductivity type upper epitaxial layer 20 and lower epitaxial layer 4; besides, the first conductivity buried layer 8 is provided between the above epitaxial layers 20 and 4. Such a configuration makes the effective thickness of the epitaxial layer of the photodetector part thick and improves the sensitivity of the photodetector. Further, the circuit element part allows the upper epitaxial layer to have a thickness and a concentration which optimize an operation of its circuit element part and then, speeding up of its element is achieved.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a light receiving element with a built-in circuit, which includes a light receiving element and a circuit element for processing an output signal thereof.

(Prior art) A photodetector with a built-in circuit is exploded in a process similar to that of a bipolar IC.That is, as shown in FIG. In order to reduce゜17...Full formation, further providing a P+ type diffusion layer 19 to form a light receiving element, paste 13(a),
Emitter 13(b), collector contact 13(c)i
are provided to form a circuit element. Therefore, when a photodiode, for example, is formed as a light-receiving element and an NPN transistor, for example, is formed as a circuit element, the epitaxial layers of the pixel elements have the same thickness and have the same specific resistance.

The ninth way to increase the speed of a photodetector with a built-in circuit is to lower the capacitance by increasing the resistivity of the epitaxial layer of the photodiode in the photodiode, but this will reduce the NP of the circuit element.
There is a problem in that the collector resistance of the N transistor increases, the collector saturation voltage increases, and the circuit response speed decreases.

Ninth, to increase the sensitivity of a photodiode, it is necessary to increase the thickness of the epitaxial layer. However, simply increasing the thickness will reduce the response speed of the photodiode section and reduce the NPN
) In addition to the same problems as described above, such as an increase in collector saturation voltage and a decrease in circuit response speed due to an increase in the collector resistance of the transistor, there is also the problem of an increase in chip size due to an increase in the area of the element isolation layer. To solve this problem,
For example, Japanese Patent Application Laid-Open No. 63-122164 proposes a structure similar to the third factor. This is the first publication of the above-mentioned public notice.
This corresponds to the figure. That is, the carrier concentration Q of the N-type epitaxial layer 22 formed on the high resistivity N-type semiconductor substrate 1 is set to a concentration suitable for the depletion layer of the PIN photodiode A, and furthermore, the N-type epitaxial layer 22 is
is divided into a plurality of π layers by P-type separation diffusion layers 21 and 21,
The bipolar fist device B has a fully formed part that further includes:
An N-well layer 20' (j is formed to increase the carrier concentration to a value suitable for the bivorous device B. In the figure, %16 is an N-type buried layer, 19 is an anode of the photodiode, and 23 is an N+ type buried layer. This is a mold embedding layer.

13(a) is the base of NPN) transistor, 13(b)
is an emitter, and 13(c) is a collector contact.

(Problems to be Solved by the Invention) Even in the structure as shown in FIG. 3, the problem of a reduction in the response speed of the photodiode due to a diffusion current component from the substrate of the photodiode when light is incident is not solved. As mentioned above, the conditions for the epitaxial layer required for the photodetector section and the conditions for the epitaxial layer required for the circuit element section are different, making it difficult to realize a highly sensitive and high-speed in-circuit photodetector. Ta. The present invention aims to achieve this.

(Means for Solving the Problems) In the present invention, a second conductivity type (for example, A lower epitaxial layer of a first conductivity type is grown on the surface of the buried layer of P type), a buried layer of the first conductivity type is formed in a region of the surface where the circuit element is to be formed, and Further, an upper epitaxial layer of the first conductivity type is formed on the surface, and a light-receiving element is formed in a portion where the buried layer T- is not provided between the upper epitaxial layer and the lower epitaxial layer. All circuit elements are formed in the area with the buried layer between them, and each element is separated by a layer of the second conductivity type.

(Function) According to the configuration of the present invention, the effective thickness of the epitaxial layer of the light receiving element portion can be increased, and the sensitivity of the light receiving element can be increased. Further, in the circuit element section, by making the upper epitaxial layer have the optimum thickness and concentration for the operation of the circuit element, the speed of the circuit element can be increased. Furthermore, by making the buried layer of the second conductivity type in the light receiving element part the same potential as the part (anode) of the second conductivity type on the surface of the light receiving element, the epitaxial layer in the light receiving element part is depleted in both the upper and lower directions. It is possible to prevent the response speed from decreasing due to the diffusion current component from the substrate.

(Kyuo side) An embodiment of the present invention will be described with reference to FIGS. 1(a) to (d). These show schematic cross-sectional views of each step.

As shown in FIG. 1(a), photo-roughing is applied to each of the light-receiving element intended area and the circuit element intended area on the surface of the N-type semiconductor substrate 1, and impurities are diffused into the P+ type buried layer 2.
and 3t-form.

Next, as shown in FIG. P+ type diffusion layers 5, 5 and 6.6 are formed. These separate each element. In this process, it is not necessary to reach the P+ type diffusion layers 2 and 3 from the surface at once, and it is possible to diffuse them into the interior one after another through repeated heat treatment in later steps. N+ type buried layers 7 and 8 are formed by impurity diffusion on most of the surface of the circuit element planned region. The former reduces the series resistance of the cathode of the light receiving element, and the latter reduces the series resistance of the collector of the circuit element.

After that, as shown in the same figure (c), high resistivity N was applied to the entire surface.
After growing the upper epitaxial layer 9 of the mold, the region where the circuit elements are planned is doped with impurities to form a low concentration N-type diffusion layer 20 in order to have the optimum resistivity for the circuit elements, and then each element is separated. P-type diffusion layer 10.10...
+ type diffusion layers 5, 5 and 6°6 are formed to reach the N++ type diffused layer 11 below the N+ type diffused layer 11 for the cathode of the light receiving element.
It is formed so as to reach the buried layer 7.

Next, as shown in FIG. 1(d), a P+ type diffusion layer 12i- for an anode is formed on the surface of the light receiving element part, and a base layer 13(a) of the P+ type diffusion layer, N By forming the emitter layer 13(b), which is a type diffusion layer, and the collector contact layer 13(c), which is an N+ type layer, the light receiving element with a built-in circuit of the present invention is completed.

(Effects of the Invention) According to the present invention, it is possible to use an epitaxial layer with an optimal thickness and specific resistance for each of the light receiving element and the circuit element, and furthermore, it is possible to prevent diffusion current from the substrate. A sensitive and high-speed photodetector with a built-in circuit can be obtained.

[Brief explanation of the drawing]

FIGS. 1(a) to (d) are schematic cross-sectional views of each step of an embodiment of the present invention, and FIGS. 2 and 3 are schematic cross-sectional views of a conventional example.

Claims (1)

[Claims] 1. A second conductive type formed on the surface of a semiconductor substrate of a first conductivity type.
It consists of a light-receiving element part and a circuit element part surrounded by a buried layer and a diffusion layer of the first conductivity type, and the light-receiving element part has an upper epitaxial layer and a lower epitaxial layer of the first conductivity type. 1. A light-receiving element with a built-in circuit, comprising an upper epitaxial layer and a lower epitaxial layer of a first conductivity type, and a buried layer of a first conductivity type provided between them.