JPH09260501A - Semiconductor integrated circuit with built-in photodiode - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the parasitic capacitance of a photodiode and to achieve the high speed response thereof by providing a second lightly doped separating region adjacent a separating region simultaneously with P-type diffusion. SOLUTION: An island region 13 separated by a P<+> type separating region 12 passing through an epitaxial layer is formed, and a photodiode 14 is formed in this island region 13. A second p<-> type separating region 27 doped more lightly than the separating region 12 is formed contiguously to the separating region 12 simultaneously with the selective diffusion of a P-base region 18 of an IIL 15 to obtain a structure wherein a depletion layer 28 extends within the second separating region 27.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to improving the response speed of a photodiode in a semiconductor integrated circuit incorporating the photodiode.

[0002]

2. Description of the Related Art A monolithic optical semiconductor integrated circuit device in which a photodiode, which is a light receiving element, and its peripheral circuit are integrated is manufactured separately, and a significant cost reduction can be realized as compared with a hybridized integrated circuit device. It also has a strong advantage against external noise caused by electromagnetic fields.

As a conventional optical semiconductor integrated circuit device, for example, one described in Japanese Patent Application Laid-Open No. 1-205564 is known. A conventional optical semiconductor integrated circuit device will be described with reference to FIG. In FIG. 2, 1 is a P-type semiconductor substrate, 2
Is an N-type epitaxial layer, 3 is a P + type isolation region,
4 is an N + type cathode extraction diffusion region, 5 is a cathode electrode, 6 is a silicon oxide film, and 7 is P of an NPN transistor.
A type base region, 8 is an N + type emitter region of an NPN transistor, and 9 is an N + type buried layer.

In such a structure, the P formed between the semiconductor substrate 1 and the epitaxial layer 2 surrounded by the isolation region 3 is formed.
The N junction is used as a photodiode. In this photodiode, carriers generated by light incident on the epitaxial layer 2 are detected as a current from the cathode electrode 5 in ohmic contact with the cathode extraction diffusion region 4 and used.

[0005]

However, in the optical semiconductor integrated circuit device having such a structure, the parasitic capacitance is inevitably formed by the depletion layer 10. Therefore, the larger the parasitic capacitance is, the worse the frequency characteristic of the photodiode PD becomes. There is a problem that impedes high-speed operation. Especially P + isolation region 3
In this case, since the element is formed with a relatively high impurity concentration for the purpose of separating elements, the depletion layer does not spread, which causes the parasitic capacitance to increase.

[0006]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned conventional problems, and is to form a P-type second isolation region between an epitaxial layer forming a photodiode and the isolation region. Thus, a semiconductor integrated circuit with a built-in photodiode in which the parasitic capacitance is reduced and the response speed is improved is provided.

In forming the second separation region, the P-base region of the IIL or the N-channel type M is formed.
By using the P-well region of the OSFET, the process is simplified and incorporated. According to the present invention, in addition to originally having a low impurity concentration in the epitaxial layer,
Since the P-type second isolation region is formed between the P + isolation region and the N-type epitaxial layer, the PN junction forming the photodiode becomes a P- / N-type junction, reducing the parasitic capacitance due to the depletion layer. As a result, deterioration of the frequency characteristics of the photodiode can be eliminated, and high speed operation can be realized.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings. FIG. 1 is a sectional view showing a semiconductor integrated circuit incorporating a photodiode according to the present invention. In FIG. 1, 11 is a P-type semiconductor substrate, 12 is a P + -type isolation region for separating an N-type epitaxial layer, and 13 is an island region made of an epitaxial layer separated by the P + isolation region 12. Photodiodes 14, II in each island region 13
The L15 and the NPN transistor 16 are incorporated respectively. Reference numeral 17 is an N + type cathode extraction diffusion region of the photodiode 14 formed on the surface of the island region 13, 18 is an IIL P− type base region, 19 is an IIL N + collector region, 20 is an IIL P type injector region, and 21 is an IIL. Is a P-type base contact region, 22 is a P-type base region of an NPN transistor, 23 is an N + type emitter region, 24 is an N + type collector contact region, 25 is a silicon oxide film, and 26 is an aluminum electrode.

A silicon single crystal substrate is used as the P-type semiconductor substrate 11, and when the semiconductor integrated circuit device is completed, several Ω ·
Since it has a specific resistance of cm or more and mechanically supports the semiconductor integrated circuit device, it is formed as thick as 300 μm or more. The N 1 -type epitaxial layer is grown on the semiconductor substrate 11 by phosphorus (P) doping by vapor phase epitaxy, and is laminated to have a specific resistance of several cm or more and a thickness of several μ.
This thickness is selected to be optimum depending on the incident light. The impurity concentration of the epitaxial layer is set to the optimum value for the photodiode 14, and the NPN transistor 1
On the 6 side, the isolation region 12 which may have a form in which N-type impurities are diffused in a portion serving as a collector to make up for the shortage of the impurity concentration, and , The upper diffusion layer 12b formed by diffusing downward from the surface of the epitaxial layer is connected.

The N + type cathode extraction diffusion region 17 is formed on the upper surface of the epitaxial layer at the same time as the diffusion of the emitter region 23 of the NPN transistor 16 by the selective diffusion method. An aluminum cathode electrode 16a in ohmic contact with the cathode extraction diffusion region 17
Is provided. An anode electrode 26b is provided on the surface of the P + type separation region 12 around the cathode extraction diffusion region 17.

A P- type second isolation region 27 having a lower impurity concentration than that of the isolation region 12 is formed so as to overlap the P + isolation region 12 partitioning the photodiode 14. The second isolation region 27 is formed on the substrate 11 together with the lower diffusion layer 12a of the isolation region.
A lower portion 27a formed by diffusing upward from the surface, and IIL
At the same time when the base region 18 is diffused, it is connected to the upper portion 27b formed by diffusion from the surface of the epitaxial layer. The lower portion 27a of the second separation region 27 does not necessarily need to be formed because one step is added, but the effect of the present invention is greater when it is formed. In addition, the second separation region 27 surrounds the cathode extraction diffusion region 17 and the separation region 1
It only needs to exist inside 2.

Then, a depletion layer is formed in the PN junction forming the photodiode 14 by applying a reverse bias such as +5 V between the anode electrode 26b and the cathode electrode 26a. Photocurrent is generated when light is incident on the depletion layer from the outside, and the anode / cathode electrode 26
A signal current flows through a and 26b. still,
PN junction between island region 13 and substrate 11, and island region 13
The PN junction between the first isolation region 27 and the second isolation region 27 serves as a photodiode.

FIG. 2 shows a partially enlarged view of the photodiode 14. According to the present invention, since the second isolation region 27 having a low impurity concentration is formed along the isolation region 12, the island region 1
The N-type layer 3 and the P-type layer of the second isolation region 27 form a part of the PN junction of the photodiode 14. Therefore,
The depletion layer 28 can be expanded to the side of the island region 13 which originally has a low impurity concentration, and can also be expanded to the side of the second isolation region 27 formed adjacent to the isolation region 12. Therefore, even when the same reverse bias as before is applied, the depletion layer 2
The parasitic capacitance of the photodiode having a width of 8 can be greatly reduced.

FIG. 3 is a sectional view showing a second embodiment of the present invention. The same parts as those in the previous embodiment are designated by the same reference numerals and the description thereof will be omitted. Referring to FIG. 3, an N-channel MOSFET instead of IIL is formed in an island region 13 at the center of the drawing.
30 is a BiCMOS type integrated circuit in which 30 is formed. Reference numeral 31 is a P + type buried layer, and 32 is a P− type well region. The N-channel MOSFET 30 has a well region 3
The N + type source / drain regions 33 are formed on the surface of the gate electrode 2, and the gate electrode 34 is arranged on the gate insulating film (silicon oxide film) covering the well region 32.
Similar to the previous embodiment, the upper portion 27 of the second isolation region
b is formed simultaneously with the formation of the P-type well region 32 of the N-channel MOSFET 30 by selective diffusion, and the depletion layer 28 expands inside the second isolation region 27 as well, thereby reducing the parasitic capacitance of the photodiode. be able to.

[0015]

As described above, according to the present invention, the depletion layer 28 can be expanded inside the P-type second isolation region 27 formed adjacent to the isolation region 12. It is possible to widen the width of the depletion layer 28 that spreads toward the isolation region 12 side as compared with the related art. Therefore, the parasitic capacitance of the photodiode can be reduced, and the high speed response of the photodiode can be improved.

Further, the process can be simplified by utilizing the base region 18 of the IIL or the well region 32 of the N-channel MOSFET 30.

[Brief description of drawings]

FIG. 1 is a cross-sectional view for explaining a photodiode integrated semiconductor integrated circuit of the present invention.

FIG. 2 is an enlarged cross-sectional view for explaining a photodiode integrated semiconductor integrated circuit of the present invention.

FIG. 3 is a cross-sectional view for explaining a second embodiment of the present invention.

FIG. 4 is a cross-sectional view for explaining a conventional semiconductor integrated circuit with a built-in photodiode.

Claims (3)

[Claims] 1. A semiconductor substrate of one conductivity type, an epitaxial layer of an opposite conductivity type formed on the semiconductor substrate, and one conductivity which penetrates the epitaxial layer and separates the epitaxial layer into a plurality of island regions. Type isolation region and one conductivity type IIL formed on one surface of the island region.
Of the low-concentration base region, and a reverse conductivity type I formed on the surface of the low-concentration base region.
A semiconductor device with a built-in photodiode, comprising: a collector region of IL; and a photodiode having another one of the island regions as a cathode, wherein a low concentration base of the IIL is provided between the isolation region and the island region serving as the cathode. A semiconductor integrated circuit with a built-in photodiode, wherein a second isolation region having a lower impurity concentration than the isolation region is formed simultaneously with the region. 2. A semiconductor substrate of one conductivity type, an epitaxial layer of an opposite conductivity type formed on the semiconductor substrate, and one conductivity which penetrates the epitaxial layer and separates the epitaxial layer into a plurality of island regions. Type isolation region, one conductivity type low concentration well region formed on one surface of the island region, an opposite conductivity type source / drain region formed on the surface of the low concentration well region, A semiconductor device with a built-in photodiode, comprising a gate electrode provided on a concentration well region via a gate insulating film, and a photodiode having another one of the island regions as a cathode, wherein the isolation region and the island serving as the cathode are provided. A second isolation region having an impurity concentration lower than that of the isolation region is formed at the same time as the one-conductivity-type low-concentration well region with the region. De built-in semiconductor integrated circuit. 3. The semiconductor integrated circuit with a built-in photodiode according to claim 1, wherein the second isolation region extends from the surface of the epitaxial layer to the surface of the substrate.