JP2643431B2 - Manufacturing method of high breakdown voltage semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION The present invention relates to a method of manufacturing a high-breakdown-voltage semiconductor device, and more particularly, to a method of manufacturing a semiconductor device having a region separated by a high withstand voltage from a substrate potential.

[Prior Art] When a plurality of circuit regions having a high potential difference are integrated in one semiconductor element, it is necessary to separate circuit regions having different potentials. As the separation method, there are usually two kinds of methods: dielectric separation and junction separation.

Junction isolation utilizes the reverse bias of a PN junction, and is generally used because its manufacturing cost is lower than that of dielectric isolation. FIG. 2 is a cross-sectional view of an element in a conventional example of a junction separation structure, in which a p ⁺ substrate 1 and a p ⁺ buried layer 4,
It is separated by the reverse bias of the PN junction between the p ⁺ diffusion layer 5 and the n ⁻ epitaxial layer 6 and the n ⁺ buried layer 2 surrounded by the p ⁺ diffusion layer 5. In this structure, the isolation region 7 has a high concentration of the n ⁺ buried layer 2 and
Since it is surrounded by the n ⁺ diffusion layer 3, a depletion layer does not enter the inside, and a circuit region having a higher potential than the substrate potential can be integrated in this region.

In the device having this structure, the p ⁺ diffusion layer 5 and the n ⁻ epitaxial layer 6
Between p ^- substrate 1 and n ^- epitaxial layer 6, p ^- substrate 1 and n ⁺
Substrate 1, n ^{- -} p Among although three junctions are present between the buried layer 2 between the epitaxial layer 6 is low concentration p ^- most breakdown voltage is high because it is a junction between ^- n. It is also known that the breakdown voltage between the p ⁺ diffusion layer 5 and the n ⁻ epitaxial layer 6 can be increased by the method disclosed in Japanese Patent Publication No. 61-32827. On the other hand, the breakdown voltage between the p ⁻ substrate 1 and the n ⁺ buried layer 2 is n ⁺
When the radius of curvature r _j at the end of the buried layer 2 is small, it is significantly reduced as compared with the planar bonding. For this reason, the breakdown voltage of this junction separation is determined by the breakdown voltage of the junction between the p ^- substrate 1 and the n ⁺ buried layer 2, and its value is limited to a low value.

[Problems to be Solved by the Invention] However, in order to increase the breakdown voltage of the junction between the p ⁻ substrate 1 and the n ⁺ buried layer 2 and approach the breakdown voltage of the planar junction, it is necessary to increase the radius of curvature r _j. However, this requires that the dose and diffusion time of the impurity in the n ⁺ buried layer be extremely large, and that long-time diffusion is necessary and that crystal defects are caused by the long-time diffusion. There is a limit in reality.

Accordingly, it is an object of the present invention to provide a semiconductor device which can increase the radius of curvature at the end of an n ⁺ buried layer even in a short time diffusion and has a high junction separation withstand voltage.

[Means for Solving the Problems] The present invention provides a strip-shaped diffusion portion having a narrower diffusion width toward the outer periphery in the periphery of the diffusion region of the n ⁺ buried layer, and is formed corresponding to each diffusion window. A diffusion profile that becomes shallower toward the outer periphery by diffusing so that each diffusion layer is connected to an adjacent outer diffusion layer, thereby obtaining a junction having a large radius of curvature by diffusion in a short time, thereby achieving a high isolation breakdown voltage semiconductor To get the device.

That is, according to the present invention, in a method of manufacturing a high breakdown voltage semiconductor device having a buried layer of the second conductivity type on a substrate of the first conductivity type, the outer circumference of the buried layer of the second conductivity type is narrower toward the outer periphery. It is an object of the present invention to provide a method of manufacturing a high breakdown voltage semiconductor device, characterized in that buried diffusion is performed using a plurality of diffusion windows having a diffusion width.

[Operation] A plurality of diffusion windows having a narrower diffusion width toward the outer periphery at the outer periphery of the buried layer of the second conductivity type are used. In order to perform the buried diffusion so as to be connected to the substrate, the dose of the impurity decreases toward the outer periphery, the diffusion depth becomes shallower, and the second portion having the larger radius of curvature at the outer peripheral portion of the junction surface with the substrate of the first conductivity type. A conductive type buried layer is obtained. Therefore, a semiconductor device having a high breakdown voltage can be easily manufactured.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
Note that the present invention is not limited by this.

1 (a), 1 (b) and 1 (c) show steps of manufacturing a semiconductor device having a buried layer 13 by the manufacturing method of the present invention.

First, as shown in FIG. 1A, the surface of a p ^- type Si substrate is covered with an SiO ₂ film 10, and then a diffusion window is formed by photoetching.
Open 14a, 14b, 14c, 14d. Then, diffusion of the n-type impurity is performed.

The diffusion window 14a, 14b, 14c, 14d has a narrower window width as it is closer to the outer periphery of the predetermined area.However, as the window width becomes narrower, the dose diffused through the diffusion window decreases, and the diffusion window corresponds to each diffusion window. Since the diffusion layer formed by diffusion is connected to the adjacent outer diffusion layer, the diffusion depth becomes shallower toward the outer periphery as shown by a broken line in the figure.

When the diffusion from each of these diffusion windows is superimposed, a diffusion profile as shown by a solid line is obtained, and an n ⁺ buried diffusion layer 11 having a large radius of curvature at the end is obtained. Thereafter, the SiO ₂ film 10 is removed as shown in Fig. 1 (b), after forming the p ⁺ buried diffusion layer not shown, n _- Figure 1 is grown an epitaxial layer 12 (c) As shown in the figure, the n ⁺ impurity further diffuses up and down, and the n ⁺ buried layer having a large radius of curvature at the junction surface with the p ⁻ substrate 1.
13 is obtained.

Although PN is arbitrarily described in the embodiment of the present invention, the effect of the present invention is also the same when the conductivity type is the opposite. Further, in the embodiment of the present invention, the diffusion window interval becomes wider toward the outer periphery. However, even if the diffusion window interval becomes narrower toward the outer periphery, the diffusion window interval is formed corresponding to each diffusion window. If the diffusion is performed such that each diffusion layer is connected to the adjacent outer diffusion layer, similar to the embodiment, the adjacent inner diffusion layer does not include the outer diffusion layer.
Since each diffusion layer is formed in a step-like shape, a buried layer having a large radius of curvature at the end can be formed, and the effect of the present invention can be similarly obtained.

[Effect] According to the present invention, the radius of curvature of the end of the buried layer of the second conductivity type at the junction between the substrate of the first conductivity type and the buried layer of the second conductivity type, which determines the isolation breakdown voltage of the element, is increased. Therefore, a junction-isolated semiconductor device having a high element separation withstand voltage can be manufactured.

[Brief description of the drawings]

1 (a), 1 (b) and 1 (c) are cross-sectional views of an element in each step of an embodiment of the present invention, FIG. 2 (a) is a cross-sectional view of an element in a conventional example of a junction separation structure, and FIG. ) Is FIG. 2 (a)
It is a top view of the element of FIG. 1 ... p ^- substrate, 2 ... n ⁺ buried layer, 3 ... n ₊ diffusion layer, 4 ... p ⁺ buried layer, 5 ... p ₊ diffusion layer, 6 ... n _- epitaxial layer, 7 …… isolation region, 10… SiO ₂ , 11 …… n ⁺ buried diffusion layer, 12 …… n ⁻ epitaxial layer, 13 …… n ⁺ buried layer, 14a, 14b, 14c, 14d …… diffusion window.

Claims (1)

(57) [Claims] In a method of manufacturing a high breakdown voltage semiconductor device having a buried layer of a second conductivity type on a substrate of a first conductivity type, an outer peripheral portion of the buried layer forming region of the second conductivity type is directed to an outer periphery. The diffusion of the buried layer is performed by using a plurality of diffusion windows having a narrower diffusion width so that each diffusion layer formed corresponding to each diffusion window is connected to an adjacent outer diffusion layer. Of manufacturing a high breakdown voltage semiconductor device.