JPH09283646A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To dissolve a part which increases the curvature of a depletion layer, and to increase the breakdown strength of a transistor by a method wherein a guard ring region is provided on the periphery of the base region of the transistor and field electrodes are respectively extended to each LOCOS oxide film. SOLUTION: An epitaxial layer 22 formed on a substrate 21 is isolated to form a plurality of insular regions 26 and P<+> guard ring regions 50 are respectively formed on the surface of each insular region 26. Each LOCOS oxide film 27 is formed in the vicinities of the regions 50. Field electrodes 38, which cover the upper part of the base-collector junction of an N-P-N transistor 28, are formed along with a gate electrode 35 and the field electrodes 38 are respectively provided extendedly to the upper part of each LOCOS oxide film 27.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to improvement of base-collector withstand voltage VCBO of a semiconductor integrated circuit including a bipolar transistor.

[0002]

2. Description of the Related Art In semiconductor integrated circuits (ICs, LSIs, etc.), as the miniaturization of each element progresses, the junction depth becomes shallower, so that the breakdown voltage is lowered, and a relatively high voltage is applied to such ICs. In this case, how to improve the reverse withstand voltage VCBO between the base and collector of the bipolar type transistor is an important issue.

An NPN type transistor incorporated in an IC has a P type base region formed on the surface of an N type epitaxial layer serving as a collector, and an N type emitter region formed on the surface of the base region. The depletion layer is curved inward due to surface depletion due to the base impurities (boron) being captured by the oxide film at the end of the collector junction, where electric field concentration occurs and the breakdown voltage VCBO
There was a phenomenon of deterioration.

Therefore, the applicant of the present application filed Japanese Patent Application No. 05-296.
As described in No. 691, there is proposed a method of forming a field electrode around the base region. That is, as shown in FIG. 8, a P-type base region 2 is formed on the surface of the island region 1 serving as a collector, and an N + emitter region 3 is formed on the surface of the base region 2 so as to cover the base-collector junction. Further, the field electrode 5 is formed on the oxide film 4. In this structure, since the same potential as that of the base region 2 is applied to the field electrode 5, the depletion layer can be extended to the end of the field electrode 5 and the breakdown voltage deterioration due to electric field concentration can be suppressed.

[0005]

However, even though the field electrode 5 is arranged and the depletion layer is extended, the electric field due to the field electrode is suddenly interrupted, and thus the depletion layer is also formed on the surface of the island region at the end of the field electrode 5. Since the curvature becomes large and the electric field is concentrated, the breakdown voltage is not improved more than the expected value.

[0006]

SUMMARY OF THE INVENTION The present invention has been made in view of the above conventional problems. A guard ring region is formed at a position distant from the base region, and a LOCOS oxide film is formed in the vicinity of the guard ring region. By extending the field electrode to the upper part of the LOCOS oxide film, a transistor having a large withstand voltage VCBO is obtained.

According to the present invention, the depletion layer can be extended to the guard ring region by the field electrode, and the curvature of the depletion layer can be increased in the guard ring region. Furthermore, the field electrode is L
By extending to the upper portion of the OCOS oxide film, the influence of the electric field on the silicon surface can be gradually reduced.
Therefore, the depletion layer can be terminated with a gentle curvature without sudden interruption. In addition, the LOCOS oxidation process of the MOS device,
Also, the process can be rationalized by sharing it with the gate electrode forming process.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings. FIG. 1 is a sectional view showing a semiconductor integrated circuit according to the present invention. As an example, an NPN transistor and an N channel type MOS element (hereinafter referred to as NMOS) are shown.

In FIG. 1, 21 is a P-type single crystal silicon semiconductor substrate, 22 is an N-type epitaxial layer formed on the substrate 21 by vapor phase growth, and 23 is between the substrate 21 and the epitaxial layer 22. Embedded in the N + type embedded layer, 24 is a P + type embedded layer formed by being embedded between the substrate 21 and the epitaxial layer 22, and 25 is an epitaxial layer 22 penetrating the epitaxial layer 22.
A P + type isolation region for forming a plurality of island regions 26,
Is a LOCOS oxide film formed on the surface of the epitaxial layer 22, 28 is an NPN transistor, and 29 is an NMOS element. The epitaxial layer 22 surrounded by the P + isolation region 25 and the substrate 21 is the island region 26.

The NPN transistor 28 has a P-type base region 30 formed on the surface of the island region 26, an N + -type emitter region 31 formed on the surface of the base region 30, and a collector lead-out which reaches the N + buried layer 23 from the surface of the epitaxial layer 22. Region 32. The NMOS device portion 29 includes a P− type well region 33 reaching the P + buried layer 24 from the surface of the epitaxial layer 22, an N + type source / drain region 34 formed on the surface of the well region 33, and a gate oxidation having a film thickness of several hundred angstroms. And a polysilicon gate electrode 35 formed so as to sandwich the film.

The surface of the epitaxial layer 22 is covered with a silicon oxide film 36, and an aluminum electrode 37 is in ohmic contact with each diffusion region through a contact hole formed in the oxide film 36. NPN transistor 28
Around the circumference of P
A + type guard ring region 50 is formed. The impurity concentration is higher than that of the base region 30, and the diffusion depth is also deeper than the base region 30 and the LOCOS oxide film 27. Guard ring area 50
Similarly, a LOCOS oxide film 27 is formed in the vicinity of the outer peripheral edge so as to surround the base region 30. The LOCOS oxide film 27 is a patterned oxidation resistant film (silicon nitride film)
Is formed by selective oxidation with the mask as a mask, the film thickness gradually increases from the surface of the epitaxial layer 22. The distance from the base region 30 to the LOCOS oxide film 27 is
It is almost constant over the entire circumference of the base region 30.

The surface of the island region 26 is covered with a silicon oxide film 36 having a thickness of several thousand angstroms like the gate insulating film except for the contact hole and the LOCOS oxide film 27. Then, a field electrode 38 is formed on the silicon oxide film 36 to cover at least the upper portion of the PN junction (base-collector junction) between the base region 30 and the island region 26.

Referring to FIG. 2, the field electrode 38 has an annular pattern surrounding the base region 30, and the contact hole of the base electrode 37a is expanded so that the base electrode 37a extends to the base region 30 and the field electrode. Both are in contact with 38. Further, the field electrode 38 extends over the oxide film 36 and extends over the LOCOS oxide film 27.
To the top (to the extent that the film thickness reaches or exceeds the thickest part). This field electrode is formed in the same process as the gate electrode 35 of the NMOS, and has a sheet resistance of several tens of ohms doped to reduce the gate resistance. The guard ring area 50 is also diffused and formed in an annular pattern.
The LOCOS oxide film 29 starts from the upper portion of 0.

Referring to FIG. 3A, if the field electrode 38 has a structure in which the field electrode 38 is interrupted above the oxide film 36 having a constant film thickness as in the conventional example, the electric field is interrupted suddenly, so that the depletion layer 39 is formed.
a terminates with a small curvature and generates electric field concentration. The effect of positive charges in the oxide film is added to this steep curvature, and the curvature becomes even tighter near the surface. On the other hand, when a reverse bias is applied between the base and collector in the structure of the present invention, the same potential as that of the base region 30 is applied to the field electrode 38, so that it spreads from the base-collector junction between the base region 30 and the island region 26. The depletion layer 39 is expanded outward along the surface of the epitaxial layer 22 by the electric field of the field electrode 38. The extended depletion layer 39 is the guard ring region 5
When connected to 0, the potential of the guard ring region 50 becomes equal to the base potential, and the depletion layer 39 extends along the PN junction between the guard ring region 50 and the island region 26. Since the guard ring region 50 is formed as deep as about 3 μ, the curvature of the depletion layer 39 extending along the PN junction of the guard ring region 50 can be relaxed.

As shown in FIG. 3A, the guard ring region 50 is terminated in the middle of the region (X in the figure) in which the film thickness of the LOCOS oxide film 27 gradually increases, and the filled electrode 38 is LOCOS-oxidized. If it extends to the upper part of the film 27, the influence of the electric field given to the silicon surface by the field electrode 38 gradually weakens, so that the depletion layer 39 around the guard ring region 50 is further expanded (FIG. 51) to increase the withstand voltage. Can be planned.

FIG. 4 is a sectional view showing a second embodiment of the present invention. DSA instead of the NMOS device 29 of FIG.
Type MOS element 40 (hereinafter, DMOS element) is formed. The same parts as those in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted. The DMOS element 40 has a large number of MOS cells formed in the island region 26 separated by the separation region 24.
In the figure, 41 is a P type diffusion region, 42 is an N + type source region formed on the surface of the P type diffusion region 41, and 43 is a polysilicon gate electrode.

The P type diffusion region 41 has a body portion having a high concentration and a deep diffusion depth, and a channel portion having a low concentration and a shallow diffusion depth. A voltage is applied to the gate electrode 43 to form a channel on the surface of the channel portion between the source region 42 and the island region 26, and the current between the source and drain is controlled. 44 is a drain lead-out region,
It reaches the N + buried layer 23 from the surface of the epitaxial layer 22. The DMOS element 40 is configured with the island region 26 as a common drain, and the N + buried layer 23 and the collector lead-out region 44 reduce the drain series resistance and become MOSFE.
Reduce ON resistance RDS (on) of T. Then, one set of P-type diffusion region 41 and gate electrode 43 is configured as a MOS cell, and the gates, sources, and drains of the plurality of MOS cells are commonly connected to each other to form a large current type. Collector lead-out area 44
Is arranged so as to surround the entire MOS cell, or
Alternatively, the cells are arranged so as to surround each unit number. The gate electrode 43a of the outermost peripheral cell is connected to the NPN transistor 28.
If it extends to the upper portion of the LOCOS oxide film 27 like the field electrode 38, the breakdown voltage of the DMOS element is improved. Further, the guard ring region 50 may be arranged below the LOCOS oxide film 27.

The NPN transistor portion 28 is formed by forming the field electrode 38 in the same process as the gate electrode 43 of the DMOS element 40. The same applies to horizontal MOS elements instead of vertical MOS elements. Subsequently, a method for manufacturing a semiconductor integrated circuit device according to the present invention will be described below with reference to FIGS. 5 to 7 by taking the second embodiment as an example.

First, referring to FIG. 5A, a P-type semiconductor substrate 21 is prepared. Antimony forming the N + buried layer 23 is deposited on the surface of the substrate 21, and P + is further deposited.
Boron that forms the isolation region 25 is ion-implanted. FIG.
Referring to (B), an N-type epitaxial layer 22 is formed on the substrate 21 by a vapor phase epitaxy method. Phosphorus is selectively diffused from the surface of the epitaxial layer 22 to form an N + collector lead-out region 32 and a drain lead-out region 44, and then boron is selectively diffused to form a P + isolation region 24 and the epitaxial layer 22 is junction-separated. To form the island region 26.

Further, by selectively diffusing boron on the surface of the island region 26, the NPN transistor 28 and the DMOS 4 are formed.
A guard ring region 0 of 0 is formed. Referring to FIG. 6A, a silicon nitride film is deposited and patterned on the surface of the epitaxial layer 22, and the surface of the epitaxial layer 22 is selectively oxidized using this as an oxidation resistant film to selectively LOCOS.
The oxide film 27 is formed.

Referring to FIG. 6B, a polysilicon layer is deposited on the surface of the epitaxial layer 22 by the CVD method and patterned to form a gate electrode 43 of the DMOS element section 40 and a field electrode 38 of the NPN transistor 28. To form. The resistance of the polysilicon layer is lowered by doping impurities. Referring to FIG. 7A, boron is ion-implanted and diffused by a resist mask to form a body portion of P-type diffusion region 41 of DMOS element portion 40.

Referring to FIG. 7B, boron is ion-implanted from the surface using the gate electrode 43 as a mask and diffused to form a channel portion of the P-type diffusion region 41, and then the field electrode 38 is masked. As a result, a base region 30 is formed by ion-implanting and diffusing boron into the NPN transistor 28. Further, by using the gate electrode 43 and the field electrode 38 as a mask to diffuse phosphorus from the surface, the emitter region 31 of the NPN transistor 28 and the DM
The source region 42 of the OS element 40 is formed. After that, each electrode is arranged to obtain the structure shown in FIG.

By using the steps of forming the LOCOS oxide film 27 and the gate electrode 43, the field electrode 38 can be formed without any additional step.

[0024]

As described above, according to the present invention, since the guard ring region is formed so as to surround the NPN transistor 28 and the field electrode 38 is extended to the guard ring region, the depletion layer 39 of the depletion layer 39 is formed. It is possible to reduce the curvature and increase the breakdown voltage. Further, the field electrode 38
Is extended to above the LOCOS oxide film 27, the electric field applied by the field electrode 38 can be gradually weakened, and the depletion layer 39 extending from the base-collector junction can be reduced.
Can be further expanded and terminated with a gentle curvature. Therefore, the part where the electric field concentration occurs can be released,
The VCBO of the NPN transistor 28 can be increased.

Further, the field electrode 38 and the LOCOS.
Since the process of the BiMOS structure can be shared with the oxide film 27, the process can be rationalized.

[Brief description of drawings]

FIG. 1 is a sectional view for explaining a semiconductor integrated circuit of the present invention.

FIG. 2 is a plan view for explaining a semiconductor integrated circuit of the present invention.

FIG. 3 is a cross-sectional view illustrating a semiconductor integrated circuit of the present invention.

FIG. 4 is a cross-sectional view for explaining the second embodiment of the present invention.

FIG. 5 is a cross-sectional view for explaining the method for manufacturing a semiconductor integrated circuit of the present invention.

FIG. 6 is a cross-sectional view for explaining the method for manufacturing a semiconductor integrated circuit of the present invention.

FIG. 7 is a cross-sectional view for explaining the method for manufacturing a semiconductor integrated circuit of the present invention.

FIG. 8 is a sectional view for explaining a conventional optical semiconductor integrated circuit.

Claims (5)

[Claims] 1. A semiconductor substrate of one conductivity type, an epitaxial layer of the opposite conductivity type formed on the semiconductor substrate, and an isolation region of one conductivity type that penetrates the epitaxial layer to form a plurality of island regions. A base region of one conductivity type formed on the surface of the island region, an emitter region of opposite conductivity type formed on the surface of the base region, and a base region surrounding the base region at a position away from the base region. A guard ring region of one conductivity type formed on the surface of the island region, an insulating film that covers the surface of the island region and has a film thickness that gradually increases from near the upper portion of the guard ring region, the base region and the island. A semiconductor integrated circuit, comprising: a field electrode that covers an upper portion of a PN junction with a region and extends to an upper portion of an insulating film whose film thickness gradually increases. 2. The semiconductor integrated circuit according to claim 1, wherein the field electrode is a polysilicon layer. 3. The insulating film whose thickness gradually increases is LO
2. The semiconductor integrated circuit according to claim 1, which is a COS oxide film. 4. A semiconductor integrated circuit in which a bipolar type element and a MOS type element are integrated on the same semiconductor substrate, wherein a one conductivity type semiconductor substrate and a reverse conductivity type formed on the semiconductor substrate. Type epitaxial layer, one conductivity type isolation region penetrating the epitaxial layer to form a plurality of island regions, a LOCOS oxide film formed on the surface of the epitaxial layer, and a LOCOS oxide film formed on the surface of the epitaxial layer. A source / drain region; a gate electrode disposed between the source region and the drain region via a gate insulating film; a base region of one conductivity type formed on one surface of the island region; An emitter region of the opposite conductivity type formed on the surface of the region, and an emitter region formed on the surface of the island region so as to surround the base region at a position distant from the base region. A conductive type guard ring region and the LOCOS oxide film are formed in the vicinity of the guard ring region, are formed simultaneously with the gate electrode, and cover an upper portion of a PN junction between the base region and the island region, LOCOS
A semiconductor integrated circuit, comprising: a field electrode extending to an upper portion of an oxide film. 5. A semiconductor integrated circuit in which a bipolar type element and a MOS type element are integrated on the same semiconductor substrate, wherein a one conductivity type semiconductor substrate and a reverse conductivity type formed on the semiconductor substrate. Type epitaxial layer, one conductivity type isolation region penetrating the epitaxial layer to form a plurality of island regions, a LOCOS oxide film formed on the surface of the epitaxial layer, and a LOCOS oxide film formed on the surface of the epitaxial layer. A diffusion region of one conductivity type, a source region of opposite conductivity type formed on the surface of the diffusion region of one conductivity type, a gate electrode arranged in the vicinity of the source region, and one formed on one surface of the island region. A conductive type base region, an opposite conductive type emitter region formed on the surface of the base region, and the island so as to surround the base region at a position distant from the base region. A one-conductivity-type guard ring region formed on the surface of the region, the LOCOS oxide film is formed in the vicinity of the guard ring region, and is formed simultaneously with the gate electrode, and the PN of the base region and the island region is formed. Covering the top of the junction, said LOCOS
A semiconductor integrated circuit, comprising: a field electrode extending to an upper portion of an oxide film.