CN105448733A - Depletion type VDMOS device and manufacturing method thereof - Google Patents
Depletion type VDMOS device and manufacturing method thereof Download PDFInfo
- Publication number
- CN105448733A CN105448733A CN201410444009.1A CN201410444009A CN105448733A CN 105448733 A CN105448733 A CN 105448733A CN 201410444009 A CN201410444009 A CN 201410444009A CN 105448733 A CN105448733 A CN 105448733A
- Authority
- CN
- China
- Prior art keywords
- layer
- conduction type
- source region
- groove
- well region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 31
- XHXFXVLFKHQFAL-UHFFFAOYSA-N phosphoryl trichloride Chemical compound ClP(Cl)(Cl)=O XHXFXVLFKHQFAL-UHFFFAOYSA-N 0.000 claims abstract description 32
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 18
- 229910052751 metal Inorganic materials 0.000 claims abstract description 13
- 239000002184 metal Substances 0.000 claims abstract description 13
- 238000005530 etching Methods 0.000 claims abstract description 10
- 230000003647 oxidation Effects 0.000 claims abstract description 7
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 7
- 238000000034 method Methods 0.000 claims description 23
- -1 boron ion Chemical class 0.000 claims description 19
- 229920005591 polysilicon Polymers 0.000 claims description 12
- 229910052796 boron Inorganic materials 0.000 claims description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 230000015572 biosynthetic process Effects 0.000 claims description 7
- 108090000723 Insulin-Like Growth Factor I Proteins 0.000 claims description 4
- 102000013275 Somatomedins Human genes 0.000 claims description 4
- 239000011521 glass Substances 0.000 claims description 3
- 238000002347 injection Methods 0.000 claims description 3
- 239000007924 injection Substances 0.000 claims description 3
- 235000012239 silicon dioxide Nutrition 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- 238000001259 photo etching Methods 0.000 abstract description 4
- 230000010354 integration Effects 0.000 abstract 1
- 230000000149 penetrating effect Effects 0.000 abstract 1
- 238000000407 epitaxy Methods 0.000 description 9
- 238000005516 engineering process Methods 0.000 description 5
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical group [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical group [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
- H01L29/7828—Vertical transistors without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66666—Vertical transistors
Abstract
The invention discloses a depletion type VDMOS device and a manufacturing method thereof. The manufacturing method comprises the steps of growing an oxidation layer on an epitaxial layer, manufacturing first conductive type well regions on the oxidized epitaxial layer, forming a photoetching pattern on the oxidation layer through a photoetching manner, etching along the photoetching pattern, etching troughs and penetrating the first conductive type well regions, carrying out N-type doping on the troughs by using phosphorus oxychloride, growing a gate oxidation layer on the epitaxial layer, growing a polycrystalline silicon layer on the gate oxidation layer, etching the polycrystalline silicon layer on the troughs, manufacturing second conductive type source regions on the epitaxial layer, growing a dielectric layer on the epitaxial layer, and forming contact holes and a metal layers to form a trough type depletion VDMOS. Therefore, the manufacturing method effectively reduces production cost, reduces device area, and is more conductive to the integration and miniaturization of the system.
Description
Technical field
The present invention relates to semiconductor chip fabrication process technical field, particularly relate to a kind of depletion type VDMOS (Verticaldouble-diffusedmetaloxidesemiconductor, vertical DMOS transistor) device and manufacture method thereof.
Background technology
At present, because V-grooveMOS and U-grooveMOS is formed by corrosion V groove and U groove in numerous classification of MOS, technology difficulty is large, be difficult to accurately control, VDMOS passes through polysilicon self aligned process, accurate control gate channel length is carried out by twice Impurity Diffusion, technique is comparatively simple, and VDMOS to have switching loss little, input impedance is high, driving power is little, advantages such as transconductance linearity is good and be widely used in various field, comprise electric machine speed regulation, inverter, uninterrupted power supply, Switching Power Supply, electronic switch, high-fidelity music center, car electrics and electric ballast etc.
Low-voltage VDMOS is one of current comparatively conventional power semiconductor, and it has, and switching speed is fast, reliability is high, input impedance advantages of higher, has a very wide range of applications in electronic applications.And the slot type structure of low-voltage VDMOS, owing to eliminating the neck region resistance of plane VDMOS, greatly reduces conducting resistance, add cellular density, improve the current handling capability of power semiconductor, for this reason, groove-shaped low-voltage VDMOS has extraordinary market prospects.
VDMOS is divided into again enhancement mode VDMOS and depletion type VDMOS, but for depletion type VDMOS, only has plane in currently available technology, and plane VDMOS is mainly used in high pressure scene.And for low pressure scene, use the depletion type VDMOS of plane not only to add production cost, and due to planarized structure area comparatively large, hinder integrated, the miniaturization of system.
Therefore, how to reduce the production cost of low pressure depletion type VDMOS, reduce device area and become a technical problem being badly in need of solving.
Summary of the invention
For solving the problems of the technologies described above, the invention provides a kind of depletion type VDMOS device and manufacture method thereof, thus effectively reducing production cost, reduce device area, be more conducive to the integrated and miniaturized of system.
The present embodiment provides the manufacture method of a kind of depletion type VDMOS, comprising:
Epitaxial loayer grows oxide layer;
Epitaxial loayer after described oxidation makes the first conduction type well region;
By photolithographicallpatterned in described oxide layer, form litho pattern, etch along described litho pattern, etching groove also passes described first conduction type well region;
By phosphorus oxychloride, described groove is carried out N-type doping;
Grow gate oxide on said epitaxial layer there, growing polycrystalline silicon layer on described gate oxide, by the polysilicon layer etching above described groove;
Make the second conduction type source region on said epitaxial layer there;
Somatomedin layer form contact hole and metal level on said epitaxial layer there.
Preferably, the growth temperature of described oxide layer is 900 ~ 1100 DEG C, and thickness is 0.05 ~ 0.20um.
The oxide layer grown at temperature within the scope of this is comparatively even, is beneficial to the stability of device.
Preferably, described making first conduction type well region and the first conduction type source region, be specially:
First conduction type well region injects boron ion and forms P-tagma;
Second conduction type source region is injected phosphonium ion and is formed N-type source region.
Wherein, the dosage that boron ion is injected in P-tagma is 1.0E13 ~ 1.0E14/cm2, and energy is 80KEV ~ 120KEV, and drive in temperature and be about 1100 ~ 1200 DEG C, the time is about 50 ~ 200min.
Wherein, inject phosphonium ion, dosage is 1.0E15 ~ 1.0E16/cm2, and energy is 80KEV ~ 150KEV.
Preferably, when described groove is carried out N-type doping by described phosphorus oxychloride, its furnace tube temperature is 700 ~ 1000 DEG C.
Preferably, described growth of gate oxide layer temperature about 900 ~ 1100 DEG C, thickness is 0.02 ~ 0.20um;
Polysilicon layer growth temperature about 500 ~ 700 DEG C, thickness is 0.1 ~ 0.3um.
Preferably,
Described injection boron ion, dosage is 1.0E13 ~ 1.0E14/cm2, and energy is 80KEV ~ 120KEV, and temperature is 1100 ~ 1200 DEG C, and the time is 50 ~ 200min;
Preferably,
Described dielectric layer structure is plain 0.2um silicon dioxide and 0.8um phosphorosilicate glass.
The present invention also provides a kind of depletion type VDMOS device, comprise: epitaxial loayer, growth oxide layer on said epitaxial layer there, the the second conduction type source region generated on said epitaxial layer there, groove in above-mentioned oxide layer, gate oxide, grows the polysilicon layer on gate oxide, first conduction type well region, dielectric layer, contact hole and metal level:
Groove phosphorus oxychloride in described oxide layer is carried out N-type doping and is formed.
Preferably, described oxidated layer thickness is 0.05 ~ 0.20um, and growth temperature is 900 ~ 1100 DEG C.
Preferably, described making first conduction type well region and the first conduction type source region, be specially:
First conduction type well region is the P-tagma injecting the formation of boron ion;
Second conduction type source region is the N-type source region injecting phosphonium ion formation.
Preferably, described trench wall phosphorus oxychloride is obtained by carrying out N-type doping when 700 ~ 1000 DEG C at furnace tube temperature.
The invention provides a kind of depletion type VDMOS device and manufacture method thereof, this method is by carrying out N-type doping by phosphorus oxychloride to trench wall thus forming groove-shaped depletion type VDMOS, effective reduction production cost, reduces device area, is more conducive to the integrated and miniaturized of system.
Accompanying drawing explanation
Fig. 1 is the method flow diagram that first embodiment of the invention provides;
Fig. 2 is first device profile structural representation in the depletion type VDMOS device manufacturing process that provides of the embodiment of the present invention;
Fig. 3 is second device profile structural representation in the depletion type VDMOS device manufacturing process that provides of the embodiment of the present invention;
Fig. 4 is the 3rd device profile structural representation in the depletion type VDMOS device manufacturing process that provides of the embodiment of the present invention;
Fig. 5 is the 4th device profile structural representation in the depletion type VDMOS device manufacturing process that provides of the embodiment of the present invention;
Fig. 6 is the 5th device profile structural representation in the depletion type VDMOS device manufacturing process that provides of the embodiment of the present invention;
Fig. 7 is the 6th device profile structural representation in the depletion type VDMOS device manufacturing process that provides of the embodiment of the present invention;
Fig. 8 is the 7th device profile structural representation in the depletion type VDMOS device manufacturing process that provides of the embodiment of the present invention;
Fig. 9 is the 8th device profile structural representation in the depletion type VDMOS device manufacturing process that provides of the embodiment of the present invention;
Figure 10 is the cross-sectional view of the depletion type VDMOS device that the embodiment of the present invention provides.
Embodiment
In order to make technical problem solved by the invention, technical scheme and beneficial effect clearly understand, below in conjunction with drawings and Examples, the present invention is described in more detail.Should be appreciated that specific embodiment described herein only in order to explain the present invention, be not intended to limit the present invention.
The method flow diagram of the making depletion type VDMOS that Fig. 1 provides for the embodiment of the present invention, discloses a kind of method that depletion type VDMOS device makes, comprising:
S101: grow oxide layer on epitaxial loayer;
S102: the epitaxial loayer after described oxidation makes the first conduction type well region;
S103: by photolithographicallpatterned in described oxide layer, forms litho pattern, etches along described litho pattern, and etching groove also passes described first conduction type well region;
S104: described groove is carried out N-type doping by phosphorus oxychloride;
S105: grow gate oxide on said epitaxial layer there, growing polycrystalline silicon layer on described gate oxide, by the polysilicon layer etching above described groove;
S106: make Second Type conductive source region on said epitaxial layer there;
S107: somatomedin layer form contact hole and metal level on said epitaxial layer there;
This manufacture method, epitaxial loayer grows oxide layer, and the first conduction type well region is etched through to oxide layer, and it is how residual thus form groove-shaped depletion type VDMOS to carry out N-type by phosphorus oxychloride to trench wall, effectively reduce the production cost of depletion type VDMOS, and reduce device area, be more conducive to the integrated of system and miniaturization.
Fig. 2 to Fig. 9 is the device profile map corresponding to the embodiment of the present invention groove-shaped depletion type VDMOS device manufacture method concrete steps, describes this manufacture method in detail below in conjunction with concrete device profile map:
S101, S102: in N-type epitaxy layer, generate oxide layer 22, and in oxide layer 22, make the first conduction type well region, described first conduction type well region injects boron ion to define P-tagma 23, as shown in Figure 2;
The growth temperature of described oxide layer is 900 ~ 1100 DEG C, and growth thickness is 0.05 ~ 0.2um;
The boron ion dose that the first described conduction type well region injects is 1.0E13 ~ 1.0E14/cm2, and energy is 80KEV ~ 120KEV, drives in temperature and is about 1100 ~ 1200 DEG C. the time is about 50 ~ 200min.
S103: carry out photoetching in described oxide layer, forms litho pattern, etches along described litho pattern, etching groove 31 also passes described P-tagma, whole groove 31 is through oxide layer 22, P-tagma 23 as shown in Figure 3, and to N-type epitaxy layer, but not through N-type epitaxy layer.
S104: described groove 31 inwall is carried out N-type doping by phosphorus oxychloride, forms N-type doped region 41, forms the raceway groove of depletion type VDMOS, as shown in Figure 4;
The long temperature of described doping is 700 ~ 1000 DEG C;
S105: grow gate oxide 51 after step s 104 in above-mentioned N-type epitaxy layer, as shown in Figure 5;
Described, gate oxide 51 growth temperature about 900 ~ 1100 DEG C, thickness is 0.02 ~ 0.20um;
Growing polycrystalline silicon 52 on described gate oxide 51, as shown in Figure 5;
Described polysilicon 52 growth temperature about 500 ~ 700 DEG C, thickness is 0.1 ~ 0.3um;
Polysilicon 52 beyond in described groove is etched away, and makes the plane of the polysilicon 52 in groove lower than gate oxide 51 plane, as shown in Figure 6;
S106: make Second Type conductive source region in described N-type epitaxy layer, described Second Type conductive source region is the N+ type source region 71 injecting phosphonium ion formation, injects phosphonium ion, and dosage is 1.0E15 ~ 1.0E16/cm2, energy is 80KEV ~ 150KEV, as shown in Figure 7;
S107: somatomedin layer 81 in described N-type epitaxy layer also forms contact hole, described dielectric layer structure is that " plain silicon dioxide 0.2um+ phosphorosilicate glass 0.8um, as shown in Figure 8, makes metal level 91, as shown in Figure 9;
Described metal level comprises front metal layer and metal layer on back, and wherein, the material of front metal layer is aluminium, silicon, copper alloy, and the material of metal layer on back is titanium, nickel, silver-colored composite bed.
Can be found out by the present embodiment, of the present inventionly in the groove-shaped depletion type VDMOS process of making, etch groove, and N-type doping carried out to trench wall phosphorus oxychloride, thus defined the raceway groove of depletion type VDMOS.The present invention effectively reduces production cost, reduces device area, is more conducive to the integrated and miniaturized of system.
The present invention also provides a kind of depletion type VDMOS device, and its preferred section of structure as shown in Figure 10, comprising:
N-type epitaxy layer 21, the oxide layer of growth in described N-type epitaxy layer 21, the first conductive-type well region that N-type epitaxy layer 21 generates, groove in above-mentioned oxide layer, gate oxide 51, polysilicon 52, the second conduction type source region of growth on gate oxide, dielectric layer 81, contact hole and metal level 91:
Trench wall phosphorus oxychloride in described oxide layer is carried out N-type doping and is formed.
Preferably, described oxidated layer thickness is 0.05 ~ 0.20um, and growth temperature is 900 ~ 1100 DEG C.Described oxide layer exists
Preferably, described making first conduction type well region and the second conduction type source region, be specially:
First conduction type well region is the P-tagma 23 injecting the formation of boron ion;
Second conduction type source region is the N+ source region 71 injecting phosphonium ion formation.
Preferably, described trench wall phosphorus oxychloride is obtained by carrying out N-type doping when 700 ~ 1000 DEG C at furnace tube temperature.
Obviously, those skilled in the art can carry out various change and modification to the present invention and not depart from the spirit and scope of the present invention.Like this, if these amendments of the present invention and modification belong within the scope of the claims in the present invention and equivalent technologies thereof, then the present invention is also intended to comprise these change and modification.
Claims (11)
1. a manufacture method of depletion type VDMOS, is characterized in that, comprising:
Epitaxial loayer grows oxide layer;
Epitaxial loayer after described oxidation makes the first conduction type well region;
By photolithographicallpatterned in described oxide layer, form litho pattern, etch along described litho pattern, etching groove also passes described first conduction type well region;
By phosphorus oxychloride, described groove is carried out N-type doping;
Grow gate oxide on said epitaxial layer there, growing polycrystalline silicon layer on described gate oxide, by the polysilicon layer etching above described groove;
Make the second conduction type source region on said epitaxial layer there;
Somatomedin layer form contact hole and metal level on said epitaxial layer there.
2. method according to claim 1, is characterized in that, the temperature about 900 ~ 1100 DEG C of growth oxide layer, thickness is 0.05 ~ 0.20um.
3. method according to claim 2, is characterized in that, described making first conduction type well region and the second conduction type source region, be specially:
First conduction type well region injects boron ion and forms P-tagma;
Second conduction type source region is injected phosphonium ion and is formed N-type source region.
4. method according to claim 1, is characterized in that, when described groove being carried out N-type doping by phosphorus oxychloride, its furnace tube temperature is 700 ~ 1000 DEG C.
5. method according to claim 1, is characterized in that,
Growth of gate oxide layer temperature about 900 ~ 1100 DEG C, thickness is 0.02 ~ 0.20um;
Polysilicon layer growth temperature about 500 ~ 700 DEG C, thickness is 0.1 ~ 0.3um.
6. method according to claim 3, is characterized in that,
Described injection boron ion, dosage is 1.0E13 ~ 1.0E14/cm2, and energy is 80KEV ~ 120KEV, and temperature is 1100 ~ 1200 DEG C, and the time is 50 ~ 200min;
Described injection phosphonium ion, dosage is 1.0E15 ~ 1.0E16/cm2, and energy is 80KEV ~ 150KEV.
7. method according to claim 6, is characterized in that, described dielectric layer structure is plain 0.2um silicon dioxide and 0.8um phosphorosilicate glass.
8. a depletion type VDMOS device, comprise epitaxial loayer, growth oxide layer on said epitaxial layer there, the the second conduction type source region generated on said epitaxial layer there, the groove in above-mentioned oxide layer, gate oxide, the polysilicon layer of growth on gate oxide, first conduction type well region, dielectric layer, contact hole and metal level, is characterized in that:
Groove phosphorus oxychloride in described oxide layer is carried out N-type doping and is formed.
9. device according to claim 8, is characterized in that, described oxidated layer thickness is 0.05 ~ 0.20um, and growth temperature is 900 ~ 1100 DEG C.
10. device according to claim 9, is characterized in that, described making first conduction type well region and the first conduction type source region, be specially:
First conduction type well region is the P-tagma injecting the formation of boron ion;
Second conduction type source region is the N-type source region injecting phosphonium ion formation.
11. devices according to claim 10, is characterized in that, described groove phosphorus oxychloride is obtained by carrying out N-type doping when 700 ~ 1000 DEG C at furnace tube temperature.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410444009.1A CN105448733A (en) | 2014-09-02 | 2014-09-02 | Depletion type VDMOS device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410444009.1A CN105448733A (en) | 2014-09-02 | 2014-09-02 | Depletion type VDMOS device and manufacturing method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105448733A true CN105448733A (en) | 2016-03-30 |
Family
ID=55558787
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410444009.1A Pending CN105448733A (en) | 2014-09-02 | 2014-09-02 | Depletion type VDMOS device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105448733A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108520898A (en) * | 2018-04-02 | 2018-09-11 | 北京绿能芯创电子科技有限公司 | With can modulation starting voltage Mosfet components and its manufacturing method |
| CN109887993A (en) * | 2018-07-25 | 2019-06-14 | 章美云 | Metal oxide semiconductor field effect tube and its manufacturing method |
| WO2020078315A1 (en) * | 2018-10-15 | 2020-04-23 | 无锡华润上华科技有限公司 | Trench gate depletion-type vdmos device and manufacturing method therefor |
| WO2020135464A1 (en) * | 2018-12-25 | 2020-07-02 | 无锡华润上华科技有限公司 | Trench-type vertical double diffusion metal oxide semiconductor field-effect transistor |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2458907A1 (en) * | 1979-06-12 | 1981-01-02 | Thomson Csf | Field effect transistor with adjustable pinch off voltage - has doping chosen in intermediate layer to reduce effect of parasitic bipolar transistor |
| US20060097267A1 (en) * | 2004-11-08 | 2006-05-11 | C/O Denso Corporation | Silicon carbide semiconductor device and method for manufacturing the same |
| US20090114969A1 (en) * | 2007-11-06 | 2009-05-07 | Denso Corporation | Silicon carbide semiconductor device and related manufacturing method |
| US20090311839A1 (en) * | 2008-06-17 | 2009-12-17 | Denso Corporation | Method for manufacturing silicon carbide semicondutor device having trench gate structure |
| CN103839807A (en) * | 2012-11-20 | 2014-06-04 | 北大方正集团有限公司 | Trench DMOS transistor manufacturing method and trench DMOS transistor |
-
2014
- 2014-09-02 CN CN201410444009.1A patent/CN105448733A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2458907A1 (en) * | 1979-06-12 | 1981-01-02 | Thomson Csf | Field effect transistor with adjustable pinch off voltage - has doping chosen in intermediate layer to reduce effect of parasitic bipolar transistor |
| US20060097267A1 (en) * | 2004-11-08 | 2006-05-11 | C/O Denso Corporation | Silicon carbide semiconductor device and method for manufacturing the same |
| US20090114969A1 (en) * | 2007-11-06 | 2009-05-07 | Denso Corporation | Silicon carbide semiconductor device and related manufacturing method |
| US20090311839A1 (en) * | 2008-06-17 | 2009-12-17 | Denso Corporation | Method for manufacturing silicon carbide semicondutor device having trench gate structure |
| CN103839807A (en) * | 2012-11-20 | 2014-06-04 | 北大方正集团有限公司 | Trench DMOS transistor manufacturing method and trench DMOS transistor |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108520898A (en) * | 2018-04-02 | 2018-09-11 | 北京绿能芯创电子科技有限公司 | With can modulation starting voltage Mosfet components and its manufacturing method |
| CN109887993A (en) * | 2018-07-25 | 2019-06-14 | 章美云 | Metal oxide semiconductor field effect tube and its manufacturing method |
| WO2020078315A1 (en) * | 2018-10-15 | 2020-04-23 | 无锡华润上华科技有限公司 | Trench gate depletion-type vdmos device and manufacturing method therefor |
| US11387349B2 (en) | 2018-10-15 | 2022-07-12 | Csmc Technologies Fab2 Co., Ltd. | Trench gate depletion mode VDMOS device and method for manufacturing the same |
| WO2020135464A1 (en) * | 2018-12-25 | 2020-07-02 | 无锡华润上华科技有限公司 | Trench-type vertical double diffusion metal oxide semiconductor field-effect transistor |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104716177B (en) | A kind of manufacture method for the radio frequency LDMOS device for improving electric leakage | |
| CN107316899B (en) | Semi-super junction device and manufacturing method thereof | |
| CN101404292A (en) | VDMOS device | |
| CN104934465A (en) | Super junction composition preparation method | |
| CN105448733A (en) | Depletion type VDMOS device and manufacturing method thereof | |
| CN104409507B (en) | low on-resistance VDMOS device and preparation method | |
| CN102184945A (en) | Trench type MOSFET (metal-oxide-semiconductor field effect transistor) device | |
| CN103515443B (en) | A kind of super junction power device and manufacture method thereof | |
| CN103872054B (en) | A kind of integrated device and manufacture method, discrete device, CDMOS | |
| CN101834202B (en) | N-type lateral insulated gate bipolar device capable of reducing hot carrier effect | |
| CN203288599U (en) | VDMOS device of novel structure | |
| CN105304693A (en) | LDMOS device manufacturing method | |
| CN102104023B (en) | Method for manufacturing self-aligned high voltage complementary metal oxide semiconductor (CMOS) in bipolar-CMOS-double-diffused metal oxide semiconductor (DMOS) (BCD) process | |
| CN103022125B (en) | NLDMOS device in BCD technique and manufacture method | |
| CN110676305A (en) | Vertical channel device with low gate charge characteristics and method of manufacture | |
| CN111244177A (en) | Structure and manufacturing process of groove type MOS device and electronic device | |
| CN109994550A (en) | A kind of trough grid superjunction MOS device | |
| CN103094124B (en) | The structure of fetron and manufacture method | |
| CN205564757U (en) | Ultra -low power consumption semiconductor power device | |
| CN104638004A (en) | Super-junction MOSFET (metal-oxide-semiconductor field-effect transistor) device structure | |
| CN113707549A (en) | Manufacturing method and device for reducing MOSFET substrate resistance | |
| CN102956489B (en) | Manufacture method of trench transistor | |
| CN105336612A (en) | Planar VDMOS device and manufacturing method thereof | |
| CN207993871U (en) | A kind of trough grid superjunction MOS device | |
| CN105244279A (en) | Planar VDMOS device and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20160330 |