CN109887993A - Metal oxide semiconductor field effect tube and its manufacturing method - Google Patents
Metal oxide semiconductor field effect tube and its manufacturing method Download PDFInfo
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- CN109887993A CN109887993A CN201910343518.8A CN201910343518A CN109887993A CN 109887993 A CN109887993 A CN 109887993A CN 201910343518 A CN201910343518 A CN 201910343518A CN 109887993 A CN109887993 A CN 109887993A
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0661—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Abstract
A kind of metal oxide semiconductor field effect tube and its manufacturing method, the manufacturing method includes: to provide the substrate of the first conduction type, successively the second epitaxial layer of the first epitaxial layer of one conduction type of growth regulation and the second conduction type on substrate, isolation structure is additionally provided between first epitaxial layer and the second epitaxial layer, it etches and to be formed through the second epitaxial layer and bottom extends to the groove in the first epitaxial layer from the second epi-layer surface, Surface Creation gate dielectric layer and fill polysilicon in the trench, the injection region of the first conduction type is respectively formed in the second epitaxial layer of the groove two sides.The metal oxide semiconductor field effect tube is different from the structure of INVENTIONConventional metal-oxide semiconductor field, and which obviate well regions to be led to the channel length factors of instability by long-time high temperature horizontal proliferation, improves reliability；Meanwhile new structure can also reduce the conducting resistance of device, improve switching speed, reduce power consumption.
Description
Technical field
The present invention relates to technical field of semiconductors, especially a kind of metal oxide semiconductor field effect tube and its manufacturer
Method.
Background technique
Third generation semiconductor material with wide forbidden band silicon carbide (SiC) has many spies for being different from traditional silicon semiconductor material
Point, band gap are 2.8 times of silicon, reach 3.09 electron-volts.The insulation breakdown field strength of silicon carbide is 5.3 times of silicon, high
Up to 3.2MV/CM, therefore in high voltage power device field, silicon carbide device be can be used relative to thinner outer of traditional silicon materials
Prolong layer, to reach the identical resistance to voltage levels of traditional silicon device, while possessing lower conducting resistance.Silicon carbide power device is just
Reverse characteristic is varied less with temperature and time, therefore reliability is more preferably.Silicon carbide device has good Reverse recovery special
Property, reverse recovery time section, electric current are small, and switching loss is small, can reduce the power consumption of whole system.The thermal conductivity of silicon carbide is silicon
3.3 times, be 49W/CMK, therefore, using carbofrax material manufacturing semiconductor devices and using semiconductor of the silicon as material
Device is compared, and characteristic when using under high temperature environment is more preferably.
At present in high power device application field, especially in fields such as rail traffic, new-energy automobile, photovoltaic power generations,
Requirement for power device is higher and higher, has not required nothing more than lower system power dissipation, and more stable high-temperature working performance is also right
The miniaturization of module and system proposes more harsh requirement, and silicon carbide power device, such as: metal-oxide semiconductor (MOS)
Field-effect tube (Metal-Oxide-SemiconductorField-EffectTransistor, MOSFET) collects many advantages in one
Body, therefore it is suitably applied in the field of significant power demand.
The manufacturing process flow of conventional metal oxides semiconductor field is first to grow gate oxide, then deposit polycrystalline
Silicon forms using DOPOS doped polycrystalline silicon as the gate electrode of material then by gluing, exposure, development and etching, then carries out p-type trap
The photoetching and injection in area, then so that P type trap zone horizontal proliferation is formed channel region, the horizontal proliferation area being consequently formed by High temperature diffusion
It is exactly the channel region of device, and the diffusion rate of impurity is extremely low relative to the impurity diffusion rate in silicon in silicon carbide, this makes
The step process needs to carry out the diffusion of ultra-long time at high temperature, channel length required for could being formed.
The shortcomings that method of manufacturing technology of such conventional metal oxides semiconductor field, is apparent: first,
The stability of equipment becomes more and more unstable with the extended of working time when high temperature, and then leads to the channel of horizontal proliferation
Length it is unstable, influence the basic performance of metal oxide semiconductor field effect tube, such as threshold voltage and breakdown voltage
Unstable, the electrical parameter result consistency between batch is poor, can not be mass produced.Second, it is partly led to promote metal oxide
The voltage capability of body field-effect tube, it usually needs be continuously increased the channel length of horizontal proliferation, this leads to the area of device entirety
Increase, the output quantity decline of unit wafer, cost increase.Third, the prolonged horizontal proliferation technique of high temperature is in general furnace
Tube apparatus is difficult to realize, and is needed using expensive special equipment, this greatly increases manufacturing cost.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of metal oxide semiconductor field effect tube, the metal oxides
Semiconductor field is different from the structure of INVENTIONConventional metal-oxide semiconductor field, and which obviate well regions by high for a long time
Warm horizontal proliferation leads to the channel length factors of instability, improves reliability；Meanwhile new structure can also reduce leading for device
Be powered resistance, improves switching speed, reduces power consumption.
In order to solve the above technical problems, the present invention adopts the following technical solutions: the metal oxide semiconductor field-effect
Pipe, comprising:
The substrate of first conduction type；
It is formed in the first epitaxial layer of the first conduction type of the upper surface of substrate；
It is formed in the second epitaxial layer of the second conduction type of first epitaxial layer upper surface；
Through second epitaxial layer and extend to the groove of first epitaxial layer；
It is formed in the injection region of the first conduction type in second epitaxial layer of the groove two sides；
The isolation structure being formed between first epitaxial layer and second epitaxial layer, the isolation structure face institute
Injection region is stated, and the injection region is where the upright projection region that first epi-layer surface is formed and the isolation structure
Area coincidence is comprised in the isolation structure region；
Be grown in the gate dielectric layer of the grooved inner surface and be filled in growth have it is more in the groove of the gate dielectric layer
Crystal silicon；
The gate metal layer being connect with the polysilicon；
The source metal being connect with the injection region；
The drain metal layer being connect with the lower surface of the substrate.
In addition, the present invention also provides the manufacturing method of metal oxide semiconductor field effect tube claimed, packet
Include following steps:
S1: the substrate of the first conduction type is provided；
S2: in the first epitaxial layer of one conduction type of upper surface growth regulation of the substrate；
S3: the isolation structure at least two intervals is formed on first epitaxial layer；
S4: the second of two conduction type of first epitaxial layer and at least two isolation structure upper surface growth regulation
Epitaxial layer；
S5: performing etching in the upper surface of second epitaxial layer to form groove, second described in the groove break-through outside
Prolong layer and extend in first epitaxial layer, the groove is located at the isolation of any two at least two isolation structure
Between structure；
S6: surface grows gate dielectric layer in the groove, and filling is more in the groove for having grown gate dielectric layer
Crystal silicon；
S7: being locally implanted the injection region to form the first conduction type in the second epitaxial layer of the groove two sides respectively,
The injection region is in the upright projection region that first epi-layer surface is formed and the region weight where corresponding isolation structure
It closes or is comprised in the isolation structure region；
S8: it is formed and the gate metal layer of the polysilicon contact and the source metal contacted with the injection region；
S9: the drain metal layer with the substrate following table face contact is formed.
The present invention is provided with the second epitaxial layer of the second conduction type, only need to by control the second conduction type second outside
Prolong doping concentration when layer growth, so that it may be accurately controlled channel concentration, avoid traditional technology and need to grow channel
The process that time high temperature promotes, improves the electrology characteristic of metal oxide semiconductor field effect tube, ginseng when also improving volume production
Several stability.In addition, increasing between the first epitaxial layer of the first conduction type and the second epitaxial layer of the second conduction type
Isolation structure, the isolation structure make the first epitaxial layer being located at immediately below the injection region can not be direct with the second epitaxial layer
Contact, avoids and is formed immediately below depletion region in the injection region, so that the first epitaxial layer of the first conduction type, second
The parasitic transistor that second epitaxial layer of conduction type and the injection region three-decker of the first conduction type are formed avoids transmitting
The possibility of pole and collector punch-through breakdown improves the breakdown voltage of drain-to-source, breaches the technical bottleneck of traditional handicraft.
In addition, due to the raising of breakdown voltage, the thickness of the second epitaxial layer can be reduced as far as possible, band after increasing isolation structure
The benefit come is to reduce the conducting resistance of metal oxide semiconductor field effect tube, to improve switching speed, reduces power consumption, mentions
Rise performance of the metal oxide semiconductor field effect tube under high-frequency high-power environment.Further more, by introducing groove, so that grid are situated between
Matter layer a part is genesis analysis, reduces the area of individual devices, improves the integrated level of device, so that energy in every wafer
More devices are enough produced, production cost is substantially reduced.
Detailed description of the invention
To describe the technical solutions in the embodiments of the present invention more clearly, make required in being described below to embodiment
Attached drawing is briefly described, it should be apparent that, drawings in the following description are some embodiments of the invention, for ability
For the those of ordinary skill of domain, without creative efforts, it can also be obtained according to these attached drawings other attached
Figure.
Fig. 1 is the process signal of the manufacturing method for the metal oxide semiconductor field effect tube that one embodiment of the invention provides
Figure；
Fig. 2 is the schematic diagram of the section structure for the metal oxide semiconductor field effect tube that one embodiment of the invention provides；
Fig. 3 to Figure 10 is cuing open for the forming process for the metal oxide semiconductor field effect tube that one embodiment of the invention provides
Face structural schematic diagram.
Description of symbols:
10: substrate；
10a: buried layer；
20: the first epitaxial layers；
30: isolation structure；
40: the second epitaxial layers；
50: groove；
60: gate dielectric layer；
70: polysilicon gate；
80: injection region；
90: insulating medium layer；
110: gate metal layer；
120: source metal；
130: drain metal layer.
Specific embodiment
It is clear in order to be more clear the purpose of the present invention, technical solution and advantageous effects, below in conjunction with this hair
Attached drawing in bright embodiment, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described
Embodiment is only a part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, this field
Those of ordinary skill's every other embodiment obtained without making creative work, belongs to protection of the present invention
Range.
In the description of the present invention, it should be noted that term " center ", "upper", "lower", "left", "right", "vertical",
The orientation or positional relationship of the instructions such as "horizontal", "inner", "outside" is to be based on the orientation or positional relationship shown in the drawings, or be somebody's turn to do
Invention product using when the orientation or positional relationship usually put, be merely for convenience of description of the present invention and simplification of the description, without
It is that the device of indication or suggestion meaning or element must have a particular orientation, be constructed and operated in a specific orientation, therefore not
It can be interpreted as limitation of the present invention.In addition, term " first ", " second ", " third " etc. are only used for distinguishing description, and cannot manage
Solution is indication or suggestion relative importance.
Fig. 1 and Fig. 2 is please referred to, a kind of manufacturing method of metal oxide semiconductor field effect tube comprising following steps:
S1: the substrate 10 of the first conduction type is provided；
S2: in the first epitaxial layer 20 of one conduction type of upper surface growth regulation of the substrate 10；
S3: the isolation structure 30 at least two intervals is formed on first epitaxial layer 20；
S4: in first epitaxial layer 20 and at least two isolation structures, 30 upper surface growth regulation, two conduction type
Second epitaxial layer 40；
S5: it is performed etching in the upper surface of second epitaxial layer 40 to form groove 50, described in 50 break-through of groove
It second epitaxial layer 40 and extends in first epitaxial layer 20, the groove 50 is located at least two isolation structure 30
Any two isolation structure 30 between；
S6: gate dielectric layer 60 is grown in 50 inner surface of groove, and in the groove 50 for having grown gate dielectric layer 60
Middle filling polysilicon；
S7: the injection to form the first conduction type is locally implanted in the second epitaxial layer 40 of 50 two sides of groove respectively
Area 80, the upright projection region that the injection region 80 is formed on 20 surface of the first epitaxial layer and corresponding 30 institute of isolation structure
Area coincidence or be comprised in 30 region of isolation structure；
S8: it is formed and the gate metal layer 110 of the polysilicon contact and the source metal contacted with the injection region 80
Layer 120；
S9: the drain metal layer 130 with the 10 following table face contact of substrate is formed.
The present invention is provided with the second epitaxial layer 40 of the second conduction type, only need to be by controlling the second of the second conduction type
Doping concentration when epitaxial layer 40 is grown, so that it may be accurately controlled channel concentration, thoroughly avoid traditional technology and need to ditch
Road carries out the process of long-time high temperature propulsion, improves the electrology characteristic of metal oxide semiconductor field effect tube, also improves
The stability of parameter when volume production.In addition, in the first epitaxial layer 20 of the first conduction type and the second extension of the second conduction type
Increase isolation structure 30 between layer 40, the isolation structure 30 to be located at the first epitaxial layer 20 immediately below the injection region 80
It can not directly be contacted with the second epitaxial layer 40, avoid and be formed immediately below depletion region in the injection region 80, so that first
80 3 layers of the injection region of first epitaxial layer 20 of conduction type, the second epitaxial layer 40 of the second conduction type and the first conduction type
The parasitic transistor that structure is formed avoids the possibility of emitter Yu collector punch-through breakdown, improves the breakdown of drain-to-source
Voltage breaches the technical bottleneck of traditional handicraft.In addition, due to the raising of breakdown voltage, can be incited somebody to action after increasing isolation structure 30
The thickness of second epitaxial layer 40 reduces as far as possible, and bring benefit is to reduce the conducting of metal oxide semiconductor field effect tube
Resistance reduces power consumption to improve switching speed, promotes metal oxide semiconductor field effect tube under high-frequency high-power environment
Performance.Further more, by introducing groove 50, so that 60 a part of gate dielectric layer for being covered on 50 inner surface of groove is
Genesis analysis reduces the area of individual devices, improves the integrated level of device, so that being able to produce out in every wafer more
Device, substantially reduce production cost.
With reference to the accompanying drawings, the manufacturing method of the metal oxide semiconductor field effect tube is elaborated.
Special to illustrate herein for convenience of subsequent description: first conduction type can be N-type, then, described second leads
Electric type is p-type, conversely, first conduction type may be p-type, correspondingly, second conduction type is N-type.?
In next embodiment, retouched so that first conduction type is N-type and second conduction type is p-type as an example
It states, but is defined not to this.
Referring to figure 3., it executes step S1: substrate 10 is provided.The substrate 10 is used as the MOS field
The carrier of effect pipe primarily serves the effect of support.The substrate 10 is silicon carbide substrates.Silicon carbide (SiC) is as the
Three generations's semiconductor material with wide forbidden band, has the various features for being different from traditional silicon semiconductor material, and band gap is silicon
2.8 times, reach 3.09 electron-volts；The insulation breakdown field strength of silicon carbide is 5.3 times of silicon, up to 3.2MV/CM；Silicon carbide
Thermal conductivity is 3.3 times of silicon, is 49W/CMK, therefore in high voltage power device field, silicon carbide device shows excellent property
Energy.
Specifically, the substrate 10 is the first conduction type, and in the present embodiment, first conduction type is N-type, because
This described substrate 10 is N-type semiconductor.In other embodiments, first conduction type may be p-type, therefore, described
Substrate 10 is P-type semiconductor.The N-type substrate 10 can be formed by silicon carbide doped nitrogen or P elements, herein not
It limits.In the silicon carbide doped nitrogen, with nitrogen (N2) it is used as doped source；In the silicon carbide doped P elements
When, with hydrogen phosphide (PH3) it is used as doped source.
More specifically, the N-type substrate 10 is the N+ substrate 10 of heavy doping.The effect of heavy doping is to reduce the substrate 10
Resistance because the back side of the substrate 10 as electrode leads to client, reduces its resistance and the metal oxide half can be improved
The response speed and current capacity of conductor field-effect tube, and then the power of the metal oxide semiconductor field effect tube is promoted,
Increase its application range.Preferably, the resistivity of the N+ substrate 10 is 0.001~0.005 Ω CM.
Further, the buried layer 10a of the second conduction type is formed in the substrate 10.The quantity of the buried layer 100 can be with
It is one, or it is multiple, it is not limited thereto.When the quantity of the buried layer 10a is multiple, the multiple buried layer 10a
Between be spaced each other, between preferably the multiple buried layer 10a be equidistant interval.In addition, in the present embodiment, described second is conductive
Type is p-type, therefore the buried layer 10a is P-type semiconductor.In other embodiments, second conduction type may be N
Type, therefore, the buried layer 10a is then N-type semiconductor.The p type buried layer 10a can be by adulterating boron member in the substrate 10
Element or aluminium element are formed, and are not limited thereto.When adulterating boron element in the substrate 10, with diborane (B2H6) be used as and mix
Miscellaneous source；When adulterating aluminium element in the substrate 10, with trimethyl aluminium (TMA) or aluminium chloride (AlCl3) it is used as doped source.
Specifically, the doping way has thermal diffusion and ion implanting.In the present embodiment preferably using ion implanting
Mode.The ion implanting has purity is high, and good evenness can accurately control implantation dosage and depth, and temperature is lower, is not easy to send out
Heat defect can carry out the multiple advantages such as selective area injection as exposure mask using photoresist or metal.
Include the following steps: to cover one layer of photoetching on 10 surface of N-type substrate more specifically, forming the buried layer 10a
Glue-line (not shown) later exposes the photoresist layer as exposure mask using the mask plate with the buried layer 10a figure
Light, then develop, it is formed and the consistent window of buried layer 10a figure on the photoresist layer；With the photoresist layer
As exposure mask, local doping is carried out to the N-type substrate 10 from the window of the photoresist layer by the way of ion implanting, and
So that the 10 regional area transoid of N-type substrate becomes p-type, that is, form the p type buried layer 10a.
Increased p type buried layer 10a can be with the N-type substrate 10 and the subsequent N-type in the growth of its other side of one side surface
Parasitic NPN transistor is formed between first epitaxial layer 200, when metal oxide semiconductor field effect tube drain terminal and source are connected
When, this parasitic NPN transistor is started to work, and the electric current of N-type substrate 10 can be further amplified, be improved the metal oxide
The current capacity of semiconductor field expands the application range of device.
Referring to figure 4., step S2 is executed: on 10 surface growth regulation of substrate, one epitaxial layer 20,10 surface of substrate
For the side surface for being formed with the buried layer 10a.It is appreciated that first epitaxial layer 20 is also covered on the buried layer 10a table
Face.First epitaxial layer 20 is silicon carbide epitaxial layers.
Specifically, first epitaxial layer 20 is the first conduction type, and in the present embodiment, first conduction type is
N-type, therefore the first epitaxial layer 20 is N-type semiconductor.In other embodiments, first conduction type may be p-type, because
This, first epitaxial layer 20 is P-type semiconductor.First epitaxial layer of N-type 20 can pass through silicon carbide doped nitrogen
Or P elements are formed.In the silicon carbide doped nitrogen, with nitrogen (N2) it is used as doped source；In the silicon carbide doped phosphorus
When element, with hydrogen phosphide (PH3) it is used as doped source.In the present embodiment, Nitrogen ion is preferably adulterated.
More specifically, first epitaxial layer of N-type 20 is the first epitaxial layer of N- 20 being lightly doped.The purpose being lightly doped is to protect
First epitaxial layer 20 is demonstrate,proved with biggish resistance value so that it can bear biggish voltage, to promote the metal
The breakdown voltage of oxide semiconductor field effect pipe.Further, it is also possible to be mentioned by the thickness for increasing first epitaxial layer 20
Rise the ability that first epitaxial layer 20 bears voltage.Preferably, in the present embodiment, nitrogen is adulterated in first epitaxial layer 20
The concentration of ion is 5E14~5E15CM-3, first epitaxial layer 20 with a thickness of 15~20 μm, may be implemented in the range
Breakdown voltage is 600~1200V.
Referring to figure 5., step S3: the local growth isolation structure 30 on first epitaxial layer 20 is executed.The isolation
The quantity of structure 30 is at least two, and at least two isolation structure 30 is spaced each other, keeps independent.In detail,
The isolation structure 30 is silica separation layer, and the silica separation layer is partly embedded into first epitaxial layer 20,
Its another part is protruded from 20 surface of the first epitaxial layer.Since silica has very high dielectric strength (107V/CM),
The resistance to breakdown capability of the metal oxide semiconductor field effect tube can further be promoted.In other embodiments, it is described every
There can also be the material compared with high dielectric strength to be made by other from structure 30.Preferably, in the present embodiment, the isolation junction
The quantity of structure 30 is two.
Specifically, the isolation structure 30 is formed, i.e. silica separation layer mainly includes the following steps: described first
20 surface of epitaxial layer grows layer of silicon dioxide thin layer (not shown), the preferably described thin layer of silicon dioxide with a thickness of 15~
35nm.In the present embodiment, the thickness of the thin layer of silicon dioxide is specially 20nm.Then on the thin layer of silicon dioxide surface
Deposit one layer of silicon nitride layer (not shown).In detail, it is deposited using chemical vapour deposition technique on the thin layer of silicon dioxide surface
The silicon nitride layer.Preferably, the silicon nitride layer with a thickness of 0.15~0.4 μm.In the present embodiment, the silicon nitride layer
With a thickness of 0.2 μm.Next, covering a layer photoresist layer (not shown) on the silicon nitride layer surface, use has later
The mask plate of 30 figure of isolation structure is exposed the photoresist layer as exposure mask, then develops, in the light
It is formed and the consistent window (not shown) of 30 figure of isolation structure on photoresist layer；Using the photoresist layer as exposure mask, adopt
The silicon nitride layer is performed etching with the also shape on the silicon nitride layer from the window of the photoresist layer with the mode of etching
At with the consistent opening of 30 figure of isolation structure.In detail, the method for the etching includes dry etching and wet etching.
In the present embodiment, it is preferred to use the method for wet etching.The wet etching is by chemical etching liquid and the substance that is etched
Generation chemically reacts the substance that will be etched and strips down, with preferable isotropic etching, therefore convenient for quickly removal window
The silicon nitride layer of mouth position.In addition, wet etching also have it is easy to operate, low for equipment requirements, be easily achieved mass production
The characteristics of.In more detail, in the present embodiment, it uses the method for wet etching for phosphoric acid wet etching, passes through chemical etching liquid
Phosphoric acid and nitridation pasc reaction and remove the silicon nitride layer of described the window's position.Subsequently, the silicon nitride layer surface residual is removed
Photoresist layer.Further, using the silicon nitride layer as protection medium, using the method for dry oxidation or wet oxidation in institute
State the window's position local growth silica.In the present embodiment, it is preferred to use the method for dry oxidation is in described the window's position
Grow silica.In detail, in boiler tube, be passed through oxygen, oxygen enter first epitaxial layer 20 and with described first outside
Prolong silicon carbide reactor in layer 20 and generate silica, the silica portion is to 20 growth inside of the first epitaxial layer, part
To 20 external growth of the first epitaxial layer, and form the isolation structure 30.Preferably, the isolation structure 30 with a thickness of
0.45~0.55 μm.In the present embodiment, the isolation structure 30 with a thickness of 0.5 μm.Further, the silicon nitride is removed
Layer.Specifically, the silicon nitride layer is removed using hot phosphoric acid.Further, the thin layer of silicon dioxide is removed.Specifically, make
The thin layer of silicon dioxide is removed with hydrofluoric acid solution.When removing the thin layer of silicon dioxide using the hydrofluoric acid solution,
It is realized by the time of control corrosion rate and completely removes the thin layer of silicon dioxide without destroying the isolation structure 30.It is preferred that
Ground, etching time are 60~70s.Because the thin layer of silicon dioxide thickness sole is small, when removing the thin layer of silicon dioxide pair
The isolation structure 30 hardly impacts.
Fig. 6 is please referred to, executes step S4: outside 30 surface growth regulation two of 20 surface of the first epitaxial layer and isolation structure
Prolong layer 40.Second epitaxial layer 40 is also silicon carbide epitaxial layers.When growing second epitaxial layer 40, second extension
Layer 40 is first grown in 20 surface longitudinal of the first epitaxial layer, when the thickness of second epitaxial layer 40 is more than the isolation structure
When the height on 30 protrusion 20 surfaces of the first epitaxial layer, cross growth while longitudinal growth of the second epitaxial layer 40,
Until closing up and the isolation structure 30 being completely covered.Preferably, in the present embodiment, second epitaxial layer 40 with a thickness of 10
μm。
Specifically, second epitaxial layer 40 is the second conduction type.In the present embodiment, second conduction type is
P-type, therefore second epitaxial layer 40 is P-type semiconductor.In other embodiments, second conduction type may be N
Type, therefore, second epitaxial layer 40 are then N-type semiconductor.Second epitaxial layer of p-type 40 can be by silicon carbide epitaxy
Boron element is adulterated in layer or aluminium element is formed.When adulterating boron element in silicon carbide epitaxial layers, with diborane (B2H6) be used as and mix
Miscellaneous source；When adulterating aluminium element in silicon carbide epitaxial layers, with trimethyl aluminium (TMA) or aluminium chloride (AlCl3) it is used as doped source.?
In the present embodiment, aluminium element is preferably adulterated, because comparing boron element, the aluminium element is more stable in silicon carbide, is not easy
It is influenced by high temperature and is arbitrarily spread.
More specifically, second epitaxial layer 40 is the second epitaxial layer of P- 40 being lightly doped.In detail, in the present embodiment
In, it is 5E16~1E18CM that aluminum ions concentration is adulterated in second epitaxial layer 40-3。
Fig. 7 is please referred to, step S5 is executed: groove 50, institute is performed etching and formed from the surface of second epitaxial layer 40
Groove 50 is stated through second epitaxial layer 40, and the bottom end of the groove 50 extends in first epitaxial layer 20, and position
Between described two isolation structures 30.It is appreciated that the depth of the groove 50 has to be larger than second epitaxial layer 40
Thickness just can guarantee that the bottom of the groove 50 extends in first epitaxial layer 20, and otherwise device can not work.From above-mentioned
It is found that in the present embodiment, second epitaxial layer 40 with a thickness of 10 μm, therefore, in the present embodiment, the groove 50
Depth is preferably arranged to 12 μm.The width of the groove 50 is set as 1~1.8 μm, because the width of the groove 50 is smaller then
The surface area of device is smaller, is more conducive to the integrated level for improving device, and still, smaller then its technique of the width of the groove 50 is raw
It is bigger to produce difficulty.In the present embodiment, specifically, the width of the groove 50 is set as 1.2 μm.
Specifically, the groove 50 is formed to include the following steps: first with wet oxidation in second epitaxial layer 40
Surface grows layer of silicon dioxide layer (not shown), and being laid with a layer photoresist layer in the silica layer surface later, (figure is not
Show), the photoresist layer is exposed as exposure mask using the mask plate with 50 figure of groove later, then is shown
Shadow, formation and the consistent window (not shown) of 50 figure of groove on the photoresist layer, the window is in depth direction
Between described two isolation structures 30, the groove 50 arrives nearest two in its side for the view field of (i.e. vertical direction)
The distance of isolation structure 30 can be equal or unequal；Using the photoresist layer as exposure mask, by the way of etching from
The window of the photoresist layer carries out through etching to form 1 in second epitaxial layer 40 second epitaxial layer 40
A groove 50 through second epitaxial layer 40 continues to carry out first epitaxial layer 20 later partial etching so that institute
The bottom for stating groove 50 extends in first epitaxial layer 20.In detail, the method for the etching includes dry etching and wet
Method etching.In the present embodiment, it is preferred to use the method for dry etching.The etching agent of the dry etching is plasma, benefit
With plasma and the substance reaction that is etched, volatile materials is formed, or directly bombards the substance that is etched and is allowed to be corroded, energy
Enough realize anisotropic etching, so that it is guaranteed that when making the groove 50 position of the groove 50, shape and size essence
Degree, and dry etching easily realizes that automation, treatment process are not introduced into pollution, cleannes height.In the present embodiment, the dry method is carved
Erosion is silicon carbide lithographic technique.After producing the groove 50, the photoresist layer is first removed using cleaning solution.It reuses later
Hydrofluoric acid removes the silicon dioxide layer on 40 surface of the second epitaxial layer.
Fig. 8 is please referred to, executes step S6: in a side surface of relatively described first epitaxial layer 20 of second epitaxial layer 40
And 50 inner surface of groove grows gate dielectric layer 60.The thickness of the gate dielectric layer 60 is preferably 25~50nm, in the thickness
The resistance to sparking of the metal oxide semiconductor field effect tube can be good in range.In this embodiment, it is preferred that the grid are situated between
Matter layer 60 is gate oxide, and the oxide layer is silicon dioxide layer.In other embodiments, the gate dielectric layer 60 can also be by
Other insulating materials are made, such as silicon nitride.
Specifically, it when the gate dielectric layer 60 is oxide layer, forms the gate dielectric layer 60 and includes the following steps: in life
Before the long gate dielectric layer 60, first the surface to second epitaxial layer 40 and 50 inner surface of the groove are cleaned.It is described
The effect of cleaning be to remove the various microparticle impurity of 50 inner surface of surface and the groove of second epitaxial layer 40 with
The quality of the gate dielectric layer 60 of subsequent growth is promoted, and then promotes the quality of the metal oxide semiconductor field effect tube.In detail
Carefully, the cleaning includes successively using hydrochloric acid, ammonium hydroxide, hydrogen peroxide and pure water to the surface of second epitaxial layer 40 and described
50 inner surface of groove is handled.It is raw on the surface of second epitaxial layer 40 and the groove 50 using oxidizing process after cleaning
Long gate oxide.The oxidizing process includes wet oxidation and dry oxidation.In the present embodiment, it is preferred to use dry oxidation.Institute
It states dry oxidation to refer to when growing in boiler tube, leads directly to oxygen, obstructed hydrogen, its main feature is that the growth rate of gate dielectric layer 60 is slow,
Defect is few in gate dielectric layer 60, reliable in quality.
Further, it is growing deposit polycrystalline silicon in the groove 50 for having the gate dielectric layer 60 and is forming polysilicon gate 70.
Specifically, in the 60 surface deposition polysilicon of gate dielectric layer, the polysilicon is made to fill up the groove 50, while also described
Corresponding 60 surface of gate dielectric layer in second epitaxial layer, 40 surface forms one layer of polysilicon layer.One is covered on the polysilicon layer surface
Layer photoresist layer is exposed the photoresist layer, developing forms window；The polysilicon layer is carried out by the window
Etching, the view field of the polysilicon layer left after etching in the depth direction between described two isolation structures 30, and
The polysilicon layer left after etching connect with the polysilicon in the groove 50 and collectively forms polysilicon gate 70.In other realities
It applies in example, only can also fill polysilicon in the groove 50, the polysilicon being filled in the groove 50 constitutes described more
Polysilicon gate 70.
Fig. 9 is please referred to, step S7 is executed: be locally implanted forming two independent notes in second epitaxial layer 40
Enter area 80.Described two injection regions 80 are separately positioned in the second epitaxial layer 40 of 50 two sides of groove, and described two notes
It is corresponding with described two isolation structures 30 respectively to enter area 80.In other embodiments, when the number of the isolation structure 30 is more than
At two, the number of the injection region 80 can also be with more than two, and the injection region 80 is right with the isolation structure 30 respectively
It answers.In detail, the upright projection region that the injection region 80 is formed on 20 surface of the first epitaxial layer and corresponding isolation junction
Area coincidence where structure 30, it will be understood that the upright projection that the injection region 80 is formed on 20 surface of the first epitaxial layer
The area in region is equal to the area in the region where the isolation structure 30.In other embodiments, the injection region 80 is in institute
The upright projection region for stating the formation of 20 surface of the first epitaxial layer is comprised in the region at 30 place of isolation structure, Ke Yili
Solution, area of the injection region 80 in the upright projection region that 20 surface of the first epitaxial layer is formed are greater than the isolation structure
The area in the region where 30.
In more detail, the injection region 80 is the first conduction type, and in the present embodiment, first conduction type is N
Type, therefore the injection region 80 is N-type.In other embodiments, first conduction type may be p-type, therefore, described
Injection region 80 is p-type.The N-type injection region 80 can pass through nitrogen doped local in second epitaxial layer 40 or phosphorus
Element, so that the local transoid of the second epitaxial layer 40 of the p-type becomes the injection region 80 of N-type.Preferably, in the present embodiment,
Doped chemical is nitrogen.More specifically, the concentration of doping nitrogen is higher in the injection region 80, infused described in the as N+ of heavy doping
Enter area 80, heavy doping can reduce the resistance of the injection region 80, enhance its electric conductivity.
Specifically, the injection region 80 is formed to include the following steps: to cover photoresist layer on 60 surface of gate dielectric layer
(not shown) is exposed the photoresist layer using mask plate as blocking, develops later, with the shape on the photoresist layer
At window.In the present embodiment, the position of the window and the position of the isolation structure 30 are corresponding in the depth direction, and
The shape size of the cross section of the window in the horizontal direction and the cross section of the isolation structure 30 in the horizontal direction
Shape size is consistent.In this way, can be used used when preparing the isolation structure 30 when making the injection region 80
Mask plate reduces production cost so as to reduce the production quantity of mask plate.Next, by the window, using ion
The mode of injection is injected in second epitaxial layer 40 forms the injection region 80.Then, described in being removed using cleaning solution
Photoresist layer.Subsequently, it is made annealing treatment.The annealing can be eliminated is drawn when injection forms the injection region 80
The silicon carbide lattice mismatch risen repairs damage of the doped chemical injection to silicon carbide, while can activate doped chemical.
Figure 10 is please referred to, step S8 is executed: being covered on 60 surface of gate dielectric layer and 70 surface of the polysilicon gate
Insulating medium layer 90.The insulating medium layer 90 can protect the surface of silicon carbide.In detail, the insulating medium layer
90 be the phosphorosilicate glass (BPSG) of boracic.In other embodiments, the insulating medium layer 90 is also possible to the phosphorus silicon of not boracic
Glass (PSG).In more detail, in the present embodiment, by the method for chemical vapor deposition on 60 surface of gate dielectric layer and
Insulating medium layer 90 described in 70 surface deposition of polysilicon gate.
Further, etching forms gate contact hole and source contact openings respectively in the insulating medium layer 90.The grid
The view field of pole contact hole in the depth direction is comprised in the view field of the polysilicon gate 70 in the depth direction
Interior, the quantity of the source contact openings is equal with the quantity of the injection region 80 and corresponding with injection region 80 respectively, and it is in depth
View field on degree direction is also respectively included in the view field of the injection region 80 corresponding to it in the depth direction.Tool
Body, a layer photoresist layer (not shown) is covered on 90 surface of insulating medium layer, later using with the gate contact
The mask plate of hole and source contact hole pattern is exposed the photoresist layer as exposure mask, then develops, in the light
It is formed and the gate contact hole and the consistent window (not shown) of source contact hole pattern on photoresist layer.Pass through the window pair
The insulating medium layer 90 is carried out through etching to form gate contact hole and source contact openings, at this moment, the gate contact hole
One end be the opening for being exposed to 90 surface of insulating medium layer, the other end and the polysilicon gate in the gate contact hole
Pole 70 connects, and one end of the source contact openings is the opening for being exposed to 90 surface of insulating medium layer, and the source electrode connects
The other end of contact hole is connect with the gate dielectric layer 60.More specifically, carrying out the gate dielectric layer 60 through etching, so that institute
The other end for stating source contact openings is directly connect with the injection region 80.
Further, metal is filled in the gate contact hole and source contact openings respectively and forms gate metal layer
110 and source metal 120, the gate metal layer 110 contacted with the polysilicon gate 70, the source metal 120
It is contacted respectively with corresponding injection region 80.Specifically, the step of forming the gate metal layer 110 and source metal 120 packet
It includes: filling full metal in the gate contact hole and source contact openings, while also being formed on 90 surface of insulating medium layer
One layer of metal layer.A layer photoresist layer is covered in the layer on surface of metal, the photoresist layer is exposed, developing forms window
Mouthful；The metal layer is performed etching by the window, and said metal layer is divided into three parts independent of each other,
In the metal filled in a part and the gate contact hole connect and collectively form gate metal layer 110, other two portion
Divide and is connect respectively with the metal being filled in the source contact openings and form the source metal 120.
Execute step S9: at 10 back side of substrate, i.e., the side table of described relatively described first epitaxial layer 200 of substrate 10
Face deposits one layer of metal layer, and the metal layer forms drain metal layer 130.
The foregoing is merely one embodiment of the present of invention, are not intended to limit the invention, all in essence of the invention
Within mind and principle, any modification, equivalent substitution, improvement and etc. done be should be included within the scope of the present invention.
Claims (10)
1. a kind of metal oxide semiconductor field effect tube characterized by comprising
The substrate of first conduction type；
It is formed in the first epitaxial layer of the first conduction type of the upper surface of substrate；
It is formed in the second epitaxial layer of the second conduction type of first epitaxial layer upper surface；
Through second epitaxial layer and extend to the groove of first epitaxial layer；
It is formed in the injection region of the first conduction type in second epitaxial layer of the groove two sides；
The isolation structure being formed between first epitaxial layer and second epitaxial layer is infused described in the isolation structure face
Enter area, and the injection region is in the upright projection region that first epi-layer surface is formed and the isolation structure region
It is overlapped or is comprised in the isolation structure region；
It is grown in the gate dielectric layer of the grooved inner surface and is filled in the polysilicon for growing and having in the groove of the gate dielectric layer；
The gate metal layer being connect with the polysilicon；
The source metal being connect with the injection region；
The drain metal layer being connect with the lower surface of the substrate.
2. metal oxide semiconductor field effect tube according to claim 1, which is characterized in that it further includes being formed in institute
State the buried layer of at least one the second conduction type in substrate.
3. metal oxide semiconductor field effect tube according to claim 1, which is characterized in that the isolation structure is two
Silica separation layer, described silica separation layer a part are embedded to first epitaxial layer, another part insertion described second
In epitaxial layer.
4. a kind of manufacturing method of metal oxide semiconductor field effect tube, which comprises the steps of:
S1: the substrate of the first conduction type is provided；
S2: in the first epitaxial layer of one conduction type of upper surface growth regulation of the substrate；
S3: the isolation structure at least two intervals is formed on first epitaxial layer；
S4: in the second extension of two conduction type of first epitaxial layer and at least two isolation structure upper surface growth regulation
Layer；
S5: it is performed etching in the upper surface of second epitaxial layer to form groove, the second epitaxial layer described in the groove break-through
And extend in first epitaxial layer, the groove is located at any two isolation structure at least two isolation structure
Between；
S6: surface grows gate dielectric layer in the groove, and fills polysilicon in the groove for having grown gate dielectric layer；
S7: being locally implanted the injection region to form the first conduction type in the second epitaxial layer of the groove two sides respectively, described
Injection region the upright projection region that first epi-layer surface is formed with where corresponding isolation structure area coincidence or
Person is comprised in the isolation structure region；
S8: it is formed and the gate metal layer of the polysilicon contact and the source metal contacted with the injection region；
S9: the drain metal layer with the substrate following table face contact is formed.
5. the manufacturing method of metal oxide semiconductor field effect tube according to claim 4, which is characterized in that in S1 also
Buried layer including forming at least one the second conduction type in the substrate.
6. the manufacturing method of metal oxide semiconductor field effect tube according to claim 5, which is characterized in that form institute
It states buried layer to include the following steps: to carry out local doping to the substrate of the first conduction type by the way of ion implanting, and makes
The substrate regional area transoid of first conduction type becomes the second conduction type and forms burying for second conduction type
Layer.
7. the manufacturing method of metal oxide semiconductor field effect tube according to claim 4, which is characterized in that institute in S3
Stating isolation structure is silica separation layer, and described silica separation layer a part is embedded in first epitaxial layer, another
It is protruded from first epi-layer surface part.
8. the manufacturing method of metal oxide semiconductor field effect tube according to claim 7, which is characterized in that form institute
It states silica separation layer to include the following steps: to grow thin layer of silicon dioxide in first epi-layer surface, then described two
Thin layer of silicon oxide surface deposited silicon nitride layer covers photoresist layer on the silicon nitride layer surface, described by exposing, being developed in
Silicon nitride layer surface forms the window at least two intervals, removes the silicon nitride layer at window, the photoresist layer is removed, in institute
Growth silica separation layer at window is stated, remaining silicon nitride layer is removed, removes the thin layer of silicon dioxide.
9. the manufacturing method of metal oxide semiconductor field effect tube according to claim 4, which is characterized in that shape in S5
Include the following steps: to grow layer of silicon dioxide layer in second epi-layer surface at the groove, in the silica
Form window on layer, the window vertical direction view field between any two isolation structure, from the window
Break-through etching is carried out to second epitaxial layer, continues to carry out partial etching to first epitaxial layer later, finally be etched back to
Remove the silicon dioxide layer.
10. the manufacturing method of metal oxide semiconductor field effect tube according to claim 4, which is characterized in that in S5
The width of the groove is 1~1.8 μm.
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| RU2803252C1 (en) * | 2023-03-22 | 2023-09-11 | Федеральное государственное унитарное предприятие "Российский Федеральный ядерный центр - Всероссийский научно-исследовательский институт экспериментальной физики" (ФГУП "РФЯЦ-ВНИИЭФ") | Method for manufacturing a lateral dmos transistor with an increased breakdown voltage |
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| CN113097305B (en) * | 2021-03-26 | 2022-11-08 | 深圳市金誉半导体股份有限公司 | Field-effect tube and preparation method thereof |
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| RU2803252C1 (en) * | 2023-03-22 | 2023-09-11 | Федеральное государственное унитарное предприятие "Российский Федеральный ядерный центр - Всероссийский научно-исследовательский институт экспериментальной физики" (ФГУП "РФЯЦ-ВНИИЭФ") | Method for manufacturing a lateral dmos transistor with an increased breakdown voltage |
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| CN108962978A (en) | 2018-12-07 |
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