CN105990399A - Method and device for manufacturing depletion type MOSFET - Google Patents
Method and device for manufacturing depletion type MOSFET Download PDFInfo
- Publication number
- CN105990399A CN105990399A CN201510041423.2A CN201510041423A CN105990399A CN 105990399 A CN105990399 A CN 105990399A CN 201510041423 A CN201510041423 A CN 201510041423A CN 105990399 A CN105990399 A CN 105990399A
- Authority
- CN
- China
- Prior art keywords
- type
- layer
- groove
- foreign ion
- body district
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
The invention discloses a method and a device for manufacturing a depletion type MOSFET. The method comprises the steps of implanting and driving in second type impurity ions into an active region of a first type epitaxial layer to form a second type body region; growing an oxide layer on the surface of the second type body region and etching the oxide layer; etching a groove on the upper surface of the body region, which is not covered by the oxide layer; implanting first type impurity ions for the first time on the side wall of the groove in the inclined manner to form a first type channel; removing the oxide layer; successively growing a gate oxide layer and a polycrystalline silicon layer in the groove; removing the gate oxide layer on the upper surface of the second type body region; implanting first type impurity ions for the second time on the two sides of the groove to form a source region, and successively growing a dielectric layer and a metal layer. According to the technical scheme of the invention, the depletion type MOSFET can be applied in low-voltage cases without any limitation.
Description
Technical field
The present invention relates to field of semiconductor manufacture, be specifically related to a kind of depletion type MOS tube manufacture method and
Device.
Background technology
DMOS pipe can divide into enhancement mode and depletion type two kinds.As a example by N-channel MOS pipe, enhancement mode
There is not conducting channel when zero grid bias-voltage in metal-oxide-semiconductor, it is impossible to enough conductions, raceway groove is closed type, and grid are the most electric
Pressure could form channel conduction for (more than cut-in voltage) during positive polarity;And depletion type MOS tube is inclined at zero grid
Existing for conducting channel during voltage, raceway groove is open type, needs to apply negative voltage during closedown on grid.This
Two kinds of pipe is respectively arranged with its feature and purposes.Typically, enhancement mode FET is in high speed, low consumption circuit
The sharpest edges of device can have been given play to, and owing to its grid bias-voltage polarity is identical with drain voltage, at electricity
Road is more convenient in designing, and becomes a most widely used class metal-oxide-semiconductor.Depletion type MOS tube by contrast
Also there is the feature of himself, such as, can apply to resistance switch (being equivalent to the resistance that can turn off), constant current tube
Etc. occasion, the most also possesses certain use value.
Current depletion type MOS tube is substantially plane and exhausts metal-oxide-semiconductor, for low pressure applications relatively
Few, it is restricted.Therefore, a kind of new depletion type MOS tube that can be suitable for low pressure occasion is needed badly.
Summary of the invention
The embodiment of the present invention provides manufacture method and the device of a kind of depletion type MOS tube, it is possible to achieve depletion type
Metal-oxide-semiconductor is unrestricted in low pressure applications.
The embodiment of the present invention provides the manufacture method of a kind of depletion type MOS tube, and the method includes:
Active area at first kind epitaxial layer injects Second Type foreign ion, and drives in formation Second Type
Body district;
Upper surface growth oxide layer in described Second Type body district, and etch;
The upper surface in the body district not having oxide layer is carried out etching groove;
Carry out first time of first kind foreign ion at described trenched side-wall in an inclined manner to inject, form the
One type channel, and remove removing oxide layer;
In described groove, grow gate oxide, polysilicon layer successively, and remove described Second Type body district
The gate oxide of upper surface;
The second time carrying out first kind foreign ion in described groove both sides is injected, formation source region, more successively
Somatomedin layer and metal level.
It is preferred that the described first kind is N-type, described Second Type is p-type.
It is preferred that described growing polycrystalline silicon layer also includes:
Carrying out back described polysilicon layer carving, described polysilicon layer fills up in described groove.
It is preferred that the dosage that described first kind foreign ion second time is injected is more than first kind foreign ion
The dosage injected for the first time.
The embodiment of the present invention also provides for depletion type MOS tube device, including:
The upper surface of first kind substrate is coated with first kind epitaxial layer, has in described first kind epitaxial layer
Have active area and ring region, described active area include Second Type body district, source region, first kind raceway groove and by
The groove of polysilicon layer, gate oxide composition, described source region is positioned at described groove both sides and with described first
Type channel, Second Type body district communicate, and described polysilicon layer, gate oxide fill up described groove, described
Gate oxide, between described polysilicon layer and described first kind raceway groove, sets above described groove successively
Being equipped with dielectric layer and metal level, described metal level is connected with described source region and described Second Type body district.
It is preferred that the described first kind is N-type, described Second Type is p-type.
It is preferred that the dosage of the first kind foreign ion of described source region is miscellaneous more than the first kind of described raceway groove
The dosage of matter ion.
The embodiment of the present invention shows: by first kind epitaxial layer active area inject Second Type impurity from
Son, and drive in formation Second Type body district;Grow oxide layer at described Second Type body district upper surface, and carve
Erosion;The body district upper surface not having oxide layer is carried out etching groove;Enter at described trenched side-wall in an inclined manner
The first time of row first kind foreign ion injects, and forms first kind raceway groove, and removes removing oxide layer;Institute
Gate oxide, polysilicon layer is grown successively in stating groove, and remove the upper surface in described Second Type body district
Gate oxide;The second time carrying out first kind foreign ion in described groove both sides is injected, and forms source region,
Somatomedin layer and metal level the most successively, it is possible to achieve depletion type MOS tube is unrestricted in low pressure applications.
Accompanying drawing explanation
For the technical scheme being illustrated more clearly that in the embodiment of the present invention, institute in embodiment being described below
The accompanying drawing used is needed to briefly introduce, it should be apparent that, the accompanying drawing in describing below is only the present invention's
Some embodiments, from the point of view of those of ordinary skill in the art, in the premise not paying creative work
Under, it is also possible to other accompanying drawing is obtained according to these accompanying drawings.
Fig. 1 is the manufacture method schematic flow sheet of a kind of depletion type MOS tube in the embodiment of the present invention;
Fig. 2 a to Fig. 2 g is the manufacturing flow chart of a kind of depletion type MOS tube in the embodiment of the present invention;
Fig. 3 is a kind of depletion type MOS tube device in the embodiment of the present invention.
Detailed description of the invention
In order to make the object, technical solutions and advantages of the present invention clearer, below in conjunction with accompanying drawing to this
Bright it is described in further detail, it is clear that described embodiment is only some embodiments of the present invention,
Rather than whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art are not doing
Go out all other embodiments obtained under creative work premise, broadly fall into the scope of protection of the invention.
Fig. 1 shows the manufacture method flow chart of a kind of depletion type MOS tube, and this flow process specifically includes:
Step S101, the active area at first kind epitaxial layer injects Second Type foreign ion, and drives in shape
Become Second Type body district.
Concrete, Second Type foreign ion is injected into the active area of first kind epitaxial layer, leads to the most again
Cross high temperature nitrogen flooding and enter Second Type foreign ion, form Second Type body district.
Step S102, the upper surface growth oxide layer in described Second Type body district, and etch.
Concrete, the upper surface in Second Type body district is carried out an oxidation growth oxide layer, then in this oxidation
The upper surface resist coating of layer, develops, then the portion of oxide layer that needs etch away is etched away.
Step S103, carries out etching groove to the body district upper surface not having oxide layer.
Step S104, carries out the first time note of first kind foreign ion in an inclined manner at described trenched side-wall
Enter, form first kind raceway groove 5, and remove removing oxide layer.
Concrete, under the protection of oxide layer, enter in an inclined manner on the sidewall of the groove etched
Row injects first kind foreign ion, injects first kind foreign ion for the first time and forms first kind raceway groove 5,
Then removing oxide layer is removed.Without driving in after injecting for the first time, save process procedure.
Step S105, grows gate oxide, polysilicon layer 4 in described groove successively, and removes described
The gate oxide of the upper surface of two type body region.
Concrete, grow gate oxide, polysilicon layer 4 successively according to the classical production process of metal-oxide-semiconductor, be situated between
Matter layer 2 and metal level 1, carry out back polysilicon layer 4 carving, described polysilicon layer after growing polycrystalline silicon layer 4
4 are positioned at groove, fill up described groove, across grid oxygen between described polysilicon layer 4 and first kind raceway groove 5
Change layer.
Step S106, the second time carrying out first kind foreign ion in described groove both sides is injected, and forms source
District 3, then somatomedin layer 2 and metal level 1 successively.
Concrete, the second time carrying out first kind foreign ion in described groove both sides is injected, injection from
The dosage of son, more than the dosage injected for the first time, forms source region 3, does not drives in this process.Then depend on
According to traditional technique successively somatomedin layer 2 and metal level 1
The embodiment of the present invention is passed through to inject Second Type foreign ion at the active area of first kind epitaxial layer, and
Drive in formation Second Type body district;Grow oxide layer at described Second Type body district upper surface, and etch;Right
The body district upper surface not having oxide layer carries out etching groove;First is carried out in an inclined manner at described trenched side-wall
Secondary injection first kind foreign ion forms first kind raceway groove 5, and removes removing oxide layer;Last again according to tradition
Technique grow gate oxide, polysilicon layer 4 successively, second time is injected first kind foreign ion and is formed source region
3, then somatomedin layer 2 and metal level 1 successively.Depletion type MOS tube can be realized in low pressure applications not
Restricted.
In order to enable preferably to explain the present invention, as shown in Fig. 2 a to Fig. 2 g, embodiments provide one
Planting the manufacture process of depletion type MOS tube, detailed process includes:
The substrate that the embodiment of the present invention is selected is N-type substrate, as shown in Figure 2 a, at the epitaxial layer of N-type substrate
On active area on carry out the injection to Second Type foreign ion, the i.e. injection of p type impurity ion, form P
Xing Ti district.This time inject is boron ion, and the dosage of injection is 1.0E13-9E13/cm2, it is preferable that note
The dosage entered is 5E13/cm2, energy during injection is 80KeV-150KeV.Preferably, during injection
Energy is that 100KeV effect is more preferable.Finally carry out again boron ion is driven in high temperature furnace pipe, the temperature driven in
Degree is 1150 DEG C, and the time driven in is 100-200min.
As shown in Figure 2 b, the upper surface in described PXing Ti district is carried out an oxidation growth oxide layer, then at this
The upper surface of oxide layer carries out resist coating, exposes, develops, it would be desirable to the region of etching is exposed, then uses
Dry or wet etch, etches away the oxide layer in the region exposed.
As shown in Figure 2 c, under the protection of oxide layer, the region of oxide layer is not had to perform etching in PXing Ti district,
Etch groove.The most as shown in Figure 2 d, the sidewall of the groove etched is carried out first in an inclined manner
Secondary injection first kind foreign ion forms first kind raceway groove 5, i.e. injects N-type impurity ion phosphonium ion,
The dosage now injecting phosphonium ion is 1E15-5E15/cm2, energy during injection is 80KeV-120KeV.
N-type channel 5 is formed by this process.The most as shown in Figure 2 e, after forming N-type channel 5, oxidation is removed
Layer.
As shown in figure 2f, on the basis of said structure, can under conditions of temperature is 800~1100 DEG C,
Growth thickness is the gate oxide covering of the 0.05~0.20um upper surface in aforementioned p-type body district and N-type ditch
The surface in road 5, continues under the temperature conditions of 500-800 DEG C, many with the deposit of the upper surface of above-mentioned gate oxide
Crystal silicon layer 4, then the polysilicon layer 4 to growth carries out back carving, as shown in Figure 2 g.Remove p-type body afterwards
The gate oxide of the upper surface in district, only retains the gate oxide being positioned at N-type channel 5.Then to p-type body
District carries out the injection of second time first kind foreign ion, i.e. injects phosphonium ion, the phosphonium ion now injected
Dosage, more than the dosage of the phosphonium ion of N-type channel, forms source region 3.Finally it is situated between according to traditional technique growth
Matter layer 2 and metal level 1, form a kind of depletion type MOS tube device as shown in Figure 3.
The method making depletion type MOS tube device provided based on above-described embodiment, the embodiment of the present invention also carries
Having supplied a kind of depletion type MOS tube device, this depletion type MOS tube device can be by above-mentioned making depletion type MOS
The method of pipe is made.
Based on the flow chart described in Fig. 2 a to Fig. 2 g, Fig. 3 shows that the structure of depletion type MOS tube device is shown
It is intended to, as it is shown on figure 3, this depletion type MOS tube device comprises the steps that
The upper surface of first kind substrate is coated with first kind epitaxial layer, has in described first kind epitaxial layer
Have active area and ring region, described active area include Second Type body district, source region 3, first kind raceway groove 5 and
The groove being made up of polysilicon layer 4, gate oxide, described source region 3 is positioned at described groove both sides and with described
First kind raceway groove 5, Second Type body district communicate, and described polysilicon layer 4, gate oxide fill up described groove,
Described gate oxide is between described polysilicon layer 4 and described first kind raceway groove, above described groove
It is disposed with dielectric layer 2 and metal level 1, described metal level 1 and described source region 3 and described Second Type body
District is connected.
Preferably, the described first kind is N-type, and described Second Type is p-type.
Preferably, the dosage of the first kind foreign ion of described source region 3 is more than the first kind of described raceway groove 5
The dosage of type foreign ion.
Raceway groove 5 described in the embodiment of the present invention is N-type channel 5, the metal of described depletion type MOS tube device
Layer 1 is source class, and substrate connects drain electrode, and polysilicon layer 4 is grid, when having voltage difference between drain electrode and source class,
Owing to there being the existence of N-type channel 5, therefore the depletion type MOS tube device of the embodiment of the present invention be one normally opened
Device, when grid connects nagative potential, then can make N-type channel 5 transoid is P-type layer, be equivalent at source class and
Having accessed a P-type layer between drain electrode, the electric current between source class and drain electrode can be blocked.Achieve depletion type
Metal-oxide-semiconductor is unrestricted in low pressure applications.
Although preferred embodiments of the present invention have been described, but those skilled in the art once know base
This creativeness concept, then can make other change and amendment to these embodiments.So, appended right is wanted
Ask and be intended to be construed to include preferred embodiment and fall into all changes and the amendment of the scope of the invention.
Obviously, those skilled in the art can carry out various change and modification without deviating from this to the present invention
Bright spirit and scope.So, if the present invention these amendment and modification belong to the claims in the present invention and
Within the scope of its equivalent technologies, then the present invention is also intended to comprise these change and modification.
Claims (7)
1. the manufacture method of a depletion type MOS tube, it is characterised in that the method includes:
Active area at first kind epitaxial layer injects Second Type foreign ion, and drives in formation Second Type
Body district;
Upper surface growth oxide layer in described Second Type body district, and etch;
The upper surface in the body district not having oxide layer is carried out etching groove;
Carry out first time of first kind foreign ion at described trenched side-wall in an inclined manner to inject, form the
One type channel, and remove removing oxide layer;
In described groove, grow gate oxide, polysilicon layer successively, and remove described Second Type body district
The gate oxide of upper surface;
The second time carrying out first kind foreign ion in described groove both sides is injected, formation source region, more successively
Somatomedin layer and metal level.
2. the method for claim 1, it is characterised in that the described first kind is N-type, described
Two types are p-type.
3. the method for claim 1, it is characterised in that described growing polycrystalline silicon layer also includes:
Carrying out back described polysilicon layer carving, described polysilicon layer fills up described groove.
4. the method for claim 1, it is characterised in that described first kind foreign ion second time
The dosage that the dosage injected injects for the first time more than first kind foreign ion.
5. a depletion type MOS tube device, it is characterised in that including:
The upper surface of first kind substrate is coated with first kind epitaxial layer, has in described first kind epitaxial layer
Have active area and ring region, described active area include Second Type body district, source region, first kind raceway groove and by
The groove of polysilicon layer, gate oxide composition, described source region is positioned at described groove both sides and with described first
Type channel, Second Type body district communicate, and described polysilicon layer, gate oxide fill up described groove, described
Gate oxide, between described polysilicon layer and described first kind raceway groove, sets above described groove successively
Being equipped with dielectric layer and metal level, described metal level is connected with described source region and described Second Type body district.
6. device as claimed in claim 5, it is characterised in that the described first kind is N-type, described the
Two types are p-type.
7. device as claimed in claim 5, it is characterised in that the first kind foreign ion of described source region
Dosage more than the dosage of first kind foreign ion of described raceway groove.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201510041423.2A CN105990399A (en) | 2015-01-27 | 2015-01-27 | Method and device for manufacturing depletion type MOSFET |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201510041423.2A CN105990399A (en) | 2015-01-27 | 2015-01-27 | Method and device for manufacturing depletion type MOSFET |
Publications (1)
Publication Number | Publication Date |
---|---|
CN105990399A true CN105990399A (en) | 2016-10-05 |
Family
ID=57035605
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201510041423.2A Pending CN105990399A (en) | 2015-01-27 | 2015-01-27 | Method and device for manufacturing depletion type MOSFET |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN105990399A (en) |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2458907B1 (en) * | 1979-06-12 | 1982-11-26 | Thomson Csf | |
CN101101877A (en) * | 2007-07-20 | 2008-01-09 | 哈尔滨工程大学 | Method for making groove power semiconductor device |
US20090114969A1 (en) * | 2007-11-06 | 2009-05-07 | Denso Corporation | Silicon carbide semiconductor device and related manufacturing method |
-
2015
- 2015-01-27 CN CN201510041423.2A patent/CN105990399A/en active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2458907B1 (en) * | 1979-06-12 | 1982-11-26 | Thomson Csf | |
CN101101877A (en) * | 2007-07-20 | 2008-01-09 | 哈尔滨工程大学 | Method for making groove power semiconductor device |
US20090114969A1 (en) * | 2007-11-06 | 2009-05-07 | Denso Corporation | Silicon carbide semiconductor device and related manufacturing method |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN105097682B (en) | Semiconductor devices | |
CN100411191C (en) | Transistor and method of making same | |
CN103035521B (en) | Realize the process of few groove-shaped IGBT of sub-accumulation layer | |
CN105161540A (en) | VDMOS device structure with low miller capacitance and manufacturing method of VDMOS device structure | |
CN109216276A (en) | A kind of metal-oxide-semiconductor and its manufacturing method | |
CN108649072A (en) | A kind of groove MOSFET device and its manufacturing method of low on-resistance | |
CN105655402A (en) | Low-voltage super-junction MOSFET (metal-oxide-semiconductor field effect transistor) terminal structure and method for manufacturing same | |
CN105070663B (en) | A kind of silicon carbide MOSFET raceway groove self-registered technology implementation method | |
CN103390545A (en) | Method for increasing drain-source breakdown voltage of trench NMOS and structure of trench NMOS | |
CN106684146B (en) | Grid self-aligned silicon carbide MOSFET and preparation method thereof | |
CN104966732B (en) | GaAs base pHEMT devices and preparation method thereof | |
CN208489200U (en) | Super-junction metal oxide semiconductor field effect transistor | |
CN104779164B (en) | A kind of method for improving groove-shaped VDMOS grid oxide layers breakdown voltage | |
CN206697482U (en) | A kind of trench metal-oxide semiconductor | |
CN103094124B (en) | The structure of fetron and manufacture method | |
CN105990152A (en) | VDMOS device and manufacturing method thereof | |
CN205621741U (en) | SiCMOSFET device unit | |
CN105990399A (en) | Method and device for manufacturing depletion type MOSFET | |
CN106356304A (en) | Semiconductor production process | |
CN105742179B (en) | A kind of preparation method of IGBT device | |
CN106876337A (en) | NLDMOS integrated devices and preparation method thereof | |
CN106158653A (en) | The manufacture method of plane VDMOS | |
CN103996622B (en) | A kind of method making VDMOS | |
CN206819996U (en) | A kind of new electronic component | |
CN105576021B (en) | NLDMOS device and its manufacturing method |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
RJ01 | Rejection of invention patent application after publication | ||
RJ01 | Rejection of invention patent application after publication |
Application publication date: 20161005 |