JPS57167652A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS57167652A
JPS57167652A JP4155881A JP4155881A JPS57167652A JP S57167652 A JPS57167652 A JP S57167652A JP 4155881 A JP4155881 A JP 4155881A JP 4155881 A JP4155881 A JP 4155881A JP S57167652 A JPS57167652 A JP S57167652A
Authority
JP
Japan
Prior art keywords
films
grown
silicon
layer
selectively
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4155881A
Other languages
Japanese (ja)
Other versions
JPS5938732B2 (en
Inventor
Yoshitaka Sasaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP4155881A priority Critical patent/JPS5938732B2/en
Priority to DE8282301254T priority patent/DE3265339D1/en
Priority to EP82301254A priority patent/EP0061855B1/en
Priority to US06/359,485 priority patent/US4471525A/en
Publication of JPS57167652A publication Critical patent/JPS57167652A/en
Publication of JPS5938732B2 publication Critical patent/JPS5938732B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
    • H01L21/76208—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region using auxiliary pillars in the recessed region, e.g. to form LOCOS over extended areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Bipolar Transistors (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE:To form a minute element isolating layer according to design value without conducting thermal oxidation treatment at a high temperature for a long time by selectively shaping a groove section to a base body and thermally oxidizing a semiconductor film left only to the inner circumferential surface of the groove section. CONSTITUTION:An N<+> buried layer 102 is formed selectively to the main surface of the P type silicon substrate 101, an N type silicon epitaxial layer 103 is grown, the layer 103 is thermally oxidized, and an oxide film 104 is grown. The element isolating region forming prearranged section of the film 104 is removed selectively through etching to shape opening windows, and the groove sections 106 reaching the substrate 101 are shaped. Oxide films 107 are grown onto the inner surfaces of the grooves 106, and P<+> type inversion preventive layers 108 are formed. Arsenic doped polycrystal silicon films are deposited so as to bury the groove sections 10, and silicon films 111 are left only to the surfaces of the films 107 through etching. The films 111 are changed into silicon oxide bodies 112 with approximately double thickness through thermal oxidation treatment, and the groove sections 106 are buried.
JP4155881A 1981-03-20 1981-03-20 Manufacturing method of semiconductor device Expired JPS5938732B2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP4155881A JPS5938732B2 (en) 1981-03-20 1981-03-20 Manufacturing method of semiconductor device
DE8282301254T DE3265339D1 (en) 1981-03-20 1982-03-11 Method for manufacturing semiconductor device
EP82301254A EP0061855B1 (en) 1981-03-20 1982-03-11 Method for manufacturing semiconductor device
US06/359,485 US4471525A (en) 1981-03-20 1982-03-18 Method for manufacturing semiconductor device utilizing two-step etch and selective oxidation to form isolation regions

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4155881A JPS5938732B2 (en) 1981-03-20 1981-03-20 Manufacturing method of semiconductor device

Publications (2)

Publication Number Publication Date
JPS57167652A true JPS57167652A (en) 1982-10-15
JPS5938732B2 JPS5938732B2 (en) 1984-09-19

Family

ID=12611753

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4155881A Expired JPS5938732B2 (en) 1981-03-20 1981-03-20 Manufacturing method of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5938732B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62269335A (en) * 1986-05-12 1987-11-21 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション Manufacture of semiconductor device
US5897360A (en) * 1996-10-21 1999-04-27 Nec Corporation Manufacturing method of semiconductor integrated circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62269335A (en) * 1986-05-12 1987-11-21 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション Manufacture of semiconductor device
US5897360A (en) * 1996-10-21 1999-04-27 Nec Corporation Manufacturing method of semiconductor integrated circuit

Also Published As

Publication number Publication date
JPS5938732B2 (en) 1984-09-19

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