JPS5683073A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5683073A
JPS5683073A JP15976779A JP15976779A JPS5683073A JP S5683073 A JPS5683073 A JP S5683073A JP 15976779 A JP15976779 A JP 15976779A JP 15976779 A JP15976779 A JP 15976779A JP S5683073 A JPS5683073 A JP S5683073A
Authority
JP
Japan
Prior art keywords
layer
diffusion layer
eutectic crystal
diffusion
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15976779A
Other languages
Japanese (ja)
Inventor
Atsushi Iwamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP15976779A priority Critical patent/JPS5683073A/en
Publication of JPS5683073A publication Critical patent/JPS5683073A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To obtain ohmic contact between an N type semiconductor layer and a P type semiconductor layer formed adjoining to the layer by connecting both layers through a eutectic crystal layer with metal forming a eutectic crystal with the semiconductor. CONSTITUTION:A drain (P<+> diffusion layer) D1 of a P channel MOSFET1 and a drain (N<+> diffusion layer) D2 of an N channel MOSFET2 are made up in an adjacent shape by means of oxidation, diffusion and etching processes. Metal forming a eutectic crystal with silicon such as Al is built up in only by thickness sufficient for forming the eutectic crystal such as 1,000Angstrom . Al of an unnecessary section is removed by using a normal optical etching process, leaving only an Al film of a junction section between the P<+> diffusion layer and the N<+> diffusion layer. Heat treatment sufficient for forming a eutectic crystal layer 10 is executed. Thus, the P<+> diffusion layer D1 and the N<+> diffusion layer D2 made up ohmic contact.
JP15976779A 1979-12-11 1979-12-11 Semiconductor device Pending JPS5683073A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15976779A JPS5683073A (en) 1979-12-11 1979-12-11 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15976779A JPS5683073A (en) 1979-12-11 1979-12-11 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5683073A true JPS5683073A (en) 1981-07-07

Family

ID=15700815

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15976779A Pending JPS5683073A (en) 1979-12-11 1979-12-11 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5683073A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4621276A (en) * 1984-05-24 1986-11-04 Texas Instruments Incorporated Buried contacts for N and P channel devices in an SOI-CMOS process using a single N+polycrystalline silicon layer
US4677735A (en) * 1984-05-24 1987-07-07 Texas Instruments Incorporated Method of providing buried contacts for N and P channel devices in an SOI-CMOS process using a single N+polycrystalline silicon layer
US4814853A (en) * 1981-10-28 1989-03-21 Tokyo Shibaura Denki Kabushiki Kaisha Semiconductor device with programmable fuse
US5204990A (en) * 1988-09-07 1993-04-20 Texas Instruments Incorporated Memory cell with capacitance for single event upset protection
US5250834A (en) * 1991-09-19 1993-10-05 International Business Machines Corporation Silicide interconnection with schottky barrier diode isolation

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5023786A (en) * 1973-06-30 1975-03-14
JPS5039882A (en) * 1973-07-11 1975-04-12

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5023786A (en) * 1973-06-30 1975-03-14
JPS5039882A (en) * 1973-07-11 1975-04-12

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4814853A (en) * 1981-10-28 1989-03-21 Tokyo Shibaura Denki Kabushiki Kaisha Semiconductor device with programmable fuse
US4621276A (en) * 1984-05-24 1986-11-04 Texas Instruments Incorporated Buried contacts for N and P channel devices in an SOI-CMOS process using a single N+polycrystalline silicon layer
US4677735A (en) * 1984-05-24 1987-07-07 Texas Instruments Incorporated Method of providing buried contacts for N and P channel devices in an SOI-CMOS process using a single N+polycrystalline silicon layer
US5204990A (en) * 1988-09-07 1993-04-20 Texas Instruments Incorporated Memory cell with capacitance for single event upset protection
US5250834A (en) * 1991-09-19 1993-10-05 International Business Machines Corporation Silicide interconnection with schottky barrier diode isolation

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