JPS5728353A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5728353A
JPS5728353A JP10386480A JP10386480A JPS5728353A JP S5728353 A JPS5728353 A JP S5728353A JP 10386480 A JP10386480 A JP 10386480A JP 10386480 A JP10386480 A JP 10386480A JP S5728353 A JPS5728353 A JP S5728353A
Authority
JP
Japan
Prior art keywords
layer
substrate
type
well
lack
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10386480A
Other languages
Japanese (ja)
Inventor
Tatsumi Takaira
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Kyushu Ltd
Original Assignee
NEC Kyushu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Kyushu Ltd filed Critical NEC Kyushu Ltd
Priority to JP10386480A priority Critical patent/JPS5728353A/en
Publication of JPS5728353A publication Critical patent/JPS5728353A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To improve the yield of, for example, the manufacturing process for CMOS device by gettering an impurity such as heavy metal etc through forming an N type impurity layr on the lack face of a substrate on which an element to be formed. CONSTITUTION:For example, on an N type substrate 1, a P well 2 is formed, and an N<+> type layer is formed in the well 2 and a P<+> layer 5 in the oxide film formed on the rear face of the substrate is removed, and an N<+> type impurity layer 10 is formed on the lack side by a thermal diffusion using, e.g. POCl3 to obtain a gettering layer. The forming process of the layer 10 may be also done after the P well 2 has been formed or while the N<+> type source-drain regions 4 is being formed. Also, after the layer 10 has been formed and treated at a temperature more than 800 deg.C, the layer 10, together with an oxide film 11 formed on the upper layer of the lack face, may be removed. Thus the effect of the oxide content of the heavy metal and the substrate can be lessened, and the yield can be improved.
JP10386480A 1980-07-29 1980-07-29 Manufacture of semiconductor device Pending JPS5728353A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10386480A JPS5728353A (en) 1980-07-29 1980-07-29 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10386480A JPS5728353A (en) 1980-07-29 1980-07-29 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5728353A true JPS5728353A (en) 1982-02-16

Family

ID=14365304

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10386480A Pending JPS5728353A (en) 1980-07-29 1980-07-29 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5728353A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5223734A (en) * 1991-12-18 1993-06-29 Micron Technology, Inc. Semiconductor gettering process using backside chemical mechanical planarization (CMP) and dopant diffusion

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5223734A (en) * 1991-12-18 1993-06-29 Micron Technology, Inc. Semiconductor gettering process using backside chemical mechanical planarization (CMP) and dopant diffusion

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